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Fair Chance Round Robin Arbiter

by Prateek Karanpuria
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 81 - Number 14
Year of Publication: 2013
Authors: Prateek Karanpuria
10.5120/14187-2446

Prateek Karanpuria . Fair Chance Round Robin Arbiter. International Journal of Computer Applications. 81, 14 ( November 2013), 36-40. DOI=10.5120/14187-2446

@article{ 10.5120/14187-2446,
author = { Prateek Karanpuria },
title = { Fair Chance Round Robin Arbiter },
journal = { International Journal of Computer Applications },
issue_date = { November 2013 },
volume = { 81 },
number = { 14 },
month = { November },
year = { 2013 },
issn = { 0975-8887 },
pages = { 36-40 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume81/number14/14187-2446/ },
doi = { 10.5120/14187-2446 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:56:05.293217+05:30
%A Prateek Karanpuria
%T Fair Chance Round Robin Arbiter
%J International Journal of Computer Applications
%@ 0975-8887
%V 81
%N 14
%P 36-40
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

With the advancement of Network-on-chip (NoC), fast and fair arbiter as the basic building block for high speed switches/routers gained attention in recent years. In this paper I propose the fair chance round robin arbiter (FCRRA), a high speed, low power and area efficient RRA for NoC applications. The FCRRAG tool propose in this paper can generate a design for bus arbiter, which can handle the exact number of bus masters for both on chip and off chip buses within one short cycle.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Round Robin arbiter Fair chance round robin arbiter Network on Chip iSLIP arbiter.

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