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Energy Efficient Design of Static Asymmetric Low Swing On-Chip Interconnect Circuits
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 80 - Number 15 |
| Year of Publication: 2013 |
| Authors: S. Rajendar, P. Chandrasekhar, M. Asha Rani, B. K. Pradeep Kumar Reddy |
10.5120/13940-1927
|
S. Rajendar, P. Chandrasekhar, M. Asha Rani, B. K. Pradeep Kumar Reddy . Energy Efficient Design of Static Asymmetric Low Swing On-Chip Interconnect Circuits. International Journal of Computer Applications. 80, 15 ( October 2013), 33-35. DOI=10.5120/13940-1927
Abstract
In this paper, an energy efficient design of asymmetric high performance low swing CMOS driver receiver pair for driving global on-chip interconnects is proposed. The design is implemented on 90nm CMOS technology using HSPICE. The proposed CMOS driver receiver pair reduces the power by 35. 45% as compared to the static driver with conventional level converter (CLC). The design is also compared with the asymmetric source follower driver with level converter (ASDLC), which results in high performance and low power consumption with reduced circuit complexity.
References
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