The week's pick
Random Articles
Reseach Article
Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 80 - Number 15 |
| Year of Publication: 2013 |
| Authors: G. Mareswara Rao, S. Rajendar |
10.5120/13935-1886
|
G. Mareswara Rao, S. Rajendar . Low Power Pulsed Flip-Flop using Self Driven Pass Transistor Logic. International Journal of Computer Applications. 80, 15 ( October 2013), 9-12. DOI=10.5120/13935-1886
Abstract
In this paper, a low power implicit type pulsed flip-flop (PFF) using self-driven pass transistor logic is presented. The pulse generation logic comprising of two transistor AND gate is used in the critical path of the design for improved speed and reduced complexity. The pass transistor logic driven by generated clock pulse is used directly to drive the output of the flip-flop. The proposed design is compared with the conventional implicit type data close to output (ip-DCO) flip-flop. As compared to the conventional pulse triggered flip-flop, the proposed pulsed flip-flop (PFF) design features best speed, power and power-delay-product performance. The proposed technique is implemented using HSPICE CMOS 90nm technology. The average power consumption for 50% switching activity is reduced by 12. 75% as compared to conventional ip-DCO.
References
- H. Kawaguchi, T. Sakurai, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction," IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 807-811, May 1998.
- H. Partovi, R. Burd, U. Salim, F. Weber, L. DiGregorio, D. Draper, "Flow-through latch and edge-triggered flip-flop hybrid elements", in IEEE Tech. Dig. ISSCC, pp. 138–139, 1996.
- F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald, and G. Yee, "A newfamily of semi-dynamic and dynamic flip- flops with embedded logic for high performance processors", IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 712–716, May 1999.
- J. Tschanz, S. Narendra, Z. Chen, S. Borkar, M. Sachdev, and V. De, "Comparative delay and energy of single edge-triggered and dual edge- triggered pulsed flip-flops for high performance microprocessors," in Proc. ISPLED, 2001, pp. 207–212.
- Yin-Tsung Hwang, Jin-Fa Lin, Ming-Hwa Sheu, "Low Power Pulse Triggered Flip-Flop Design With Conditional Pulse Enhancement Scheme", IEEE Trans. on Very Large Scale Integr. (VLSI). ,Vol. 20, No. 2, pp-361-366, Feb. 2012.
- Jiren Yuan, Svensson C. , "New TSPC latches and flipflops minimizing delay and power", International symposium on VLSI Circuits, pp 160-161, June 1996.
- P. Zhao, J. McNeely, W. Kaung, N. Wang, Z. Wang, "Design of sequential elements for low power clocking system," IEEE Transactions on Very Large Scale Integration (VLSI),Vol. 19, No. 5, pp 914-918, May 2011.
- P. Zhao, T. Darwish, M. Bayoumi, "High performance and low power conditional discharge flip-flop," IEEE Transactions on Very Large Scale Integr. (VLSI) Systems, vol. 12, no. 5, pp. 477–484, May 2004.
- B. Kong, S. Kim, Y. Jun, "Conditional capture flip-flop for statistical power reduction," IEEE J. Solid-State Circuits, vol. 36, no. 8, pp. 1263–1271, Aug. 2001.
Index Terms
Keywords