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FPGA based Speed Efficient Decimator using Distributed Arithmetic Algorithm
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 80 - Number 11 |
| Year of Publication: 2013 |
| Authors: Rajesh Mehra, Lajwanti Singh |
10.5120/13909-1959
|
Rajesh Mehra, Lajwanti Singh . FPGA based Speed Efficient Decimator using Distributed Arithmetic Algorithm. International Journal of Computer Applications. 80, 11 ( October 2013), 37-40. DOI=10.5120/13909-1959
Abstract
In this paper, an efficient FPGA implementation of a multipliers less decimator is presented for wireless application. DA has been used to implement a decimator taking advantage of embedded LUT based structure of FPGAs. Speed and area efficient solution is designed using half band polyphase decomposition FIR structure. The proposed decimator has been designed with MATLAB and synthesized with Xilinx synthesis tool (XST)10.1 and implemented on Spartan-3E based 3s500efg.320-4 FPGA device. Improvement of 28% in speed and 50% in area has been observed as compared to MAC based approach.
References
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