As the technology shrinks, the power consumed by links dominating the power consumed by routers. We can reduce power consumed by links by using clock gating and data encoding schemes. Clock gating is one method to reduce switching power in NoC links and we can provide this at the time of synthesis by using EDA tools. The data encoding scheme exploits the wormhole switching techniques and works on an end-to-end basis. That is, flits are encoded by the network interface (NI) before they are injected in the network and are decoded by the destination NI. This makes the scheme transparent to the underlying network since the encoder and decoder logic is integrated in the NI and no modification of the routers architecture is required Data encoding schemes are other techniques to reduce switching power in NoC links by reducing self transition and coupling transition in links. In this paper, we proposed data encoding scheme called self and coupling driven bus invert (SCDBI). By using this method we can reduce the switching power by 34. 64% without any significant degradation in area and performance.

Synthesis Coupling capacitance self capacitance data encoding low power network on chip (NoC) power analysis.