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Reseach Article
Performance Improvement of GFCAL Circuits
by
Shipra Upadhyay,
R. K. Nagaria,
R. A. Mishra
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 78 - Number 5 |
| Year of Publication: 2013 |
| Authors: Shipra Upadhyay, R. K. Nagaria, R. A. Mishra |
10.5120/13487-1193
|
Shipra Upadhyay, R. K. Nagaria, R. A. Mishra . Performance Improvement of GFCAL Circuits. International Journal of Computer Applications. 78, 5 ( September 2013), 29-37. DOI=10.5120/13487-1193
@article{
10.5120/13487-1193,
author = {
Shipra Upadhyay,
R. K. Nagaria,
R. A. Mishra
},
title = { Performance Improvement of GFCAL Circuits },
journal = {
International Journal of Computer Applications
},
issue_date = { September 2013 },
volume = { 78 },
number = { 5 },
month = { September },
year = { 2013 },
issn = { 0975-8887 },
pages = {
29-37
},
numpages = {9},
url = {
https://ijcaonline.org/archives/volume78/number5/13487-1193/
},
doi = { 10.5120/13487-1193 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:50:50.211207+05:30
%A Shipra Upadhyay
%A R. K. Nagaria
%A R. A. Mishra
%T Performance Improvement of GFCAL Circuits
%J International Journal of Computer Applications
%@ 0975-8887
%V 78
%N 5
%P 29-37
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In this paper authors have presented a new approach to improve the performance of the glitch free cascadable adiabatic logic (GFCAL) circuit by replacing the triangular power supply with sinusoidal and trapezoidal power supplies (that control the charging and discharging of the capacitive load) and by sizing of transistors. A simulative investigation and performance analysis of proposed approach based 3 bit GFCAL counter, GFCAL JK flip flop and GFCAL 6T-SRAM circuit have also been done. The triangular power supply produces very large delay at the outputs of GFCAL circuits thus it will be very difficult to cascade larger circuits. A solution to provide cascadability is optimization of the delay. In the proposed approach the delay of GFCAL counter for triangular supply has been improved about 40% and 60% whereas for JK flip flop it is 46% and 49% and for 6T SRAM it is 17% and 91% with sinusoidal and trapezoidal power clocks respectively.
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Index Terms
Computer Science
Information Sciences
Keywords