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Reseach Article

Stable and Low Power 6T SRAM

by Mamatha Samson
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 78 - Number 2
Year of Publication: 2013
Authors: Mamatha Samson
10.5120/13459-0294

Mamatha Samson . Stable and Low Power 6T SRAM. International Journal of Computer Applications. 78, 2 ( September 2013), 6-10. DOI=10.5120/13459-0294

@article{ 10.5120/13459-0294,
author = { Mamatha Samson },
title = { Stable and Low Power 6T SRAM },
journal = { International Journal of Computer Applications },
issue_date = { September 2013 },
volume = { 78 },
number = { 2 },
month = { September },
year = { 2013 },
issn = { 0975-8887 },
pages = { 6-10 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume78/number2/13459-0294/ },
doi = { 10.5120/13459-0294 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:50:34.181390+05:30
%A Mamatha Samson
%T Stable and Low Power 6T SRAM
%J International Journal of Computer Applications
%@ 0975-8887
%V 78
%N 2
%P 6-10
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper an effort is made to design a stable and energy efficient asymmetrical 6T SRAM cell in 65nm technology generation with one bit line for read and one for write operation along with dual word lines. A simple energy recovery driver is added to enhance the write ability of the SRAM and to recover energy. Sizing the access transistor helps write ability and sizing of the pull down transistor provides better read stability. This circuit saves energy during write operation and also provides good read stability.

References
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Index Terms

Computer Science
Information Sciences

Keywords

SRAM energy stability bit line