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Performance Analysis of Floating Point MAC Unit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 78 - Number 1 |
| Year of Publication: 2013 |
| Authors: Sonali Mehta, Balwinder Singh, Dilip Kumar |
10.5120/13456-1139
|
Sonali Mehta, Balwinder Singh, Dilip Kumar . Performance Analysis of Floating Point MAC Unit. International Journal of Computer Applications. 78, 1 ( September 2013), 38-41. DOI=10.5120/13456-1139
Abstract
In order to meet the requirements in real time DSP applications MAC unit is required. The speed of the MAC unit determines the overall performance of the system. MAC unit basically consists of Multiplier, adder and an accumulator unit. In most of the cases floating point adder/subtractor and a multiplier are presented in IEEE-754 format for single precision format. In this research work MAC unit is proposed. Various floating point multipliers are designed with the help of adders such as Carry look ahead, Carry save, Carry skip and then their individual performance analysis is done on the basis of power, speed, and area. Finally MAC unit is made with the help of different floating point multiplier architectures to obtain the best results in terms of area, speed and power. Various floating point multiplier architectures used in MAC unit are pipelined floating point multiplier; carry save, carry look ahead and ripple carry multipliers. All the results are calculated in Xilinx ISE 12. 4 design suite.
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