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Reseach Article

Power Reversible Comparator Circuits 180 nm Technology

by Amit Grover, Sumit Khurana
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 77 - Number 7
Year of Publication: 2013
Authors: Amit Grover, Sumit Khurana
10.5120/13403-1055

Amit Grover, Sumit Khurana . Power Reversible Comparator Circuits 180 nm Technology. International Journal of Computer Applications. 77, 7 ( September 2013), 1-4. DOI=10.5120/13403-1055

@article{ 10.5120/13403-1055,
author = { Amit Grover, Sumit Khurana },
title = { Power Reversible Comparator Circuits 180 nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { September 2013 },
volume = { 77 },
number = { 7 },
month = { September },
year = { 2013 },
issn = { 0975-8887 },
pages = { 1-4 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume77/number7/13403-1055/ },
doi = { 10.5120/13403-1055 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:49:37.032343+05:30
%A Amit Grover
%A Sumit Khurana
%T Power Reversible Comparator Circuits 180 nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 77
%N 7
%P 1-4
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This article explains design of reversible comparator circuits using GDI and TG in 180 nm technology, because of number of applications of reversible comparator [8] circuits in different fields. In this article, by combining CMOS-GDI circuit and CMOS-TG Circuits, we have implemented transistor of reversible gates. It has been observed that, usage of these techniques saves power and area as compare to CMOS implementation. GDI circuits provide some measure of enhanced hazard tolerance and are more suitable for low voltage operation [14]. Here transistor implementation of reversible gates is done by using Tanner tools and H-spice tools.

References
  1. C. H. Bennett, "Logical Reversibility of Computation", IBM J. Research and Development, pp. 525-532, November 1973.
  2. Y. -C. Hung and B. D. Liu: "1-V CMOS Comparator for Programmable Analog Rank-Order Extractor", IEEE Transactions Circuits and Systems, Vol. 50, No. 5, 2003, pp. 673-677.
  3. Lihui Ni, Zhijin Guan, Xiaoyu Dai, Wenjuan Li, "Using New Designed NLG Gate for the Realization of Four-bit Reversible Numerical Comparator", 2010 International Conference on Educational and Network Technology (ICENT 2010), 5, 978-1-4244-7662, 2010 IEEE.
  4. E. Fredkin and T. Toffoli, "Conservative logic," International Journal of Theoretical Physics, vol. 21, pp. 219–253, 1982.
  5. Arkadiy Morgenshtein, Michael Moreinis and Ran Ginosar," Asynchronous Gate-Diffusion-Input (GDI) Circuits" Very Large Scale Integration (VLSI) Systems, IEEE Journal Transactions, Aug. 2004.
  6. A. Morgenshtein, A. Fish, I. A. Wagner, "Gate-Diffusion Input (GDI) – A Novel Power Efficient Method for Digital Circuits: A Detailed Methodology," 14th IEEE International ASIC/SOC Conference, USA, September 2001.
  7. D. P. Vasudevan, P. K. Lala, J. Di and J. P. Parkerson, "Reversible-logic design with online testability", IEEE Transactions on Instrumentation and Measurement, vol. 55, no. 2, pp. 406- 414, April 2006.
  8. A N Nagamani, H V Jayashree, H R Bhagyalakshmi, "Novel Low Power Comparator Design using Reversible Logic Gates" Indian Journal of computer Science and Engineering , Vol. 2 No. 4 Aug - Sep 2011.
  9. B. Wicht, T. Nirschl and D. Schmitt-Landsiedel: "Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier", IEEE J. Solid-State Circuits, Vol. 39, No. 7, 2004, pp. 1148-1158.
  10. K. -L. J. Wong and C. -K. K. Yang: "Offset Compensation in Comparators with Minimum Input-referred supply Noise", IEEE J. Solid-State Circuits, Vol. 39, No. 5, 2004, pp. 837-840.
  11. H. J. M. Veendrick: "The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate", IEEE J. Solid-State Circuits, Vol. 15, No. 2, 1980, pp. 169-176
  12. H. P. Le, A. Zayegh, and J. Singh, "Performance analysis of optimized CMOS comparator," Electronics Letters, vol. 39, pp. 833-835, May 2003.
  13. S. Sheikhaei, S. Mirabbasi, and A. Ivanov, "A 0. 35?m CMOS Comparator Circuit for High-Speed ADC Applications," IEEE International Symposium on Circuits and Systems, pp. 6134-6137, May 2005.
  14. T. W. Matthews, P. L. Heedley, "A Simulation Method for Accurately Determining DC and Dynamic Offset in Comparators," IEEE MWSCAS, pp. 1815-1818, Aug. 2005.
  15. B. Razavi and B . A. Wooley, "Design Techniques for High-Speed High-Resolution Comparators," IEEE Journal of Solid-State Circuits, Vol-27, pp. 1916-1926, Dec 1992.
  16. A. Boni, G. Chiorboli and C. Morandi: "Dynamic characterization of high-speed latching comparators", IEEE Electron. Letters Vol. 36, No. 5, 2000, pp. 402-404.
  17. R. Feynman, "Quantum Mechanical Computers," Optics News, Vol. 11, pp. 11–20, 1985.
  18. K. Uyttenhove, M. S. J. Steyaert: "A 1. 8-V 6-Bit 1. 3-GHz Flash ADC in 0. 25-?m CMOS", IEEE J. Solid-State Circuits, Vol. 38, No. 7, July 2003, pp. 1115-1122.
Index Terms

Computer Science
Information Sciences

Keywords

Gate Diffusion Input (GDI) Transmission Gate Technology (TG).