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Reseach Article

A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors

by Manan Sethi, Karna Sharma, Paanshul Dobriyal, Navya Rajput, Geetanjali Sharma
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 77 - Number 5
Year of Publication: 2013
Authors: Manan Sethi, Karna Sharma, Paanshul Dobriyal, Navya Rajput, Geetanjali Sharma
10.5120/13393-1035

Manan Sethi, Karna Sharma, Paanshul Dobriyal, Navya Rajput, Geetanjali Sharma . A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors. International Journal of Computer Applications. 77, 5 ( September 2013), 30-35. DOI=10.5120/13393-1035

@article{ 10.5120/13393-1035,
author = { Manan Sethi, Karna Sharma, Paanshul Dobriyal, Navya Rajput, Geetanjali Sharma },
title = { A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors },
journal = { International Journal of Computer Applications },
issue_date = { September 2013 },
volume = { 77 },
number = { 5 },
month = { September },
year = { 2013 },
issn = { 0975-8887 },
pages = { 30-35 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume77/number5/13393-1035/ },
doi = { 10.5120/13393-1035 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:49:30.022280+05:30
%A Manan Sethi
%A Karna Sharma
%A Paanshul Dobriyal
%A Navya Rajput
%A Geetanjali Sharma
%T A Novel High Performance Dual Threshold Voltage Domino Logic Employing Stacked Transistors
%J International Journal of Computer Applications
%@ 0975-8887
%V 77
%N 5
%P 30-35
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Among the assorted logic styles used in fostering the integrated circuits, the domino logic styles offers higher speed and smaller transistor count as compared to the static cmos circuits. However the domino logic suffers from lower noise immunity and higher power dissipation due to the problem of charge sharing and sub-threshold leakage currents. In this paper some of the earlier proposed techniques to reduce the power consumption of the domino circuits like Dual threshold voltage (DTV) and Dual threshold voltage–voltage scaling(DTVS) have been analyzed. A novel stacked transistors Dual threshold voltage (ST-DTV) approach which deploys DTV technique with stacked transistors together with a voltage regulated static keeper is analyzed to abate the total power dissipation of the circuit together with a better Power delay product (PDP). The ST-DTV design is tested on a 3-input OR gate and a 4x1 multiplexer at 90nm technology on multiple voltages and frequencies. Tanner tool EDA v13. 0 is used for simulation.

References
  1. S. M. Kang, Y. Leblebici ,"CMOS Digital Integrated Circuits analysis and design," third edition, TMH, 2003.
  2. N. Weste and D. Harris, "CMOS VLSI Design,". Reading, MA: Addison Wesley, 2004.
  3. M. J. Mohannnadzamani, S. M. Tabatabaei and M. Fathipour, "Leakage Current Reduction in Domino Logic," in Proc. ICEE, Tehran, 2012, pp. 198-201.
  4. Y . S. Abdalla , A. A. Dessouki , and E . S. El-Badawy ,"Compensating for the Keeper Current ofCMOS Domino Logic Using a Well Designed NMOS Transistor," in Proc. NRSC, Egypt , 2009 , pp. 1-8.
  5. V. Kurson and E. G . Friedman ,"Energy Efficient Dual Threshold Voltage Dynamic Circuits Employing Sleep Switches to Minimize Subthreshold Leakage," in Proc. ISCAS, 2004, pp. 417-420.
  6. J. Wang, W. Wu, N. Gong, W. Zhang, and L. Hou, "Effectiveness Analysis of Low Power Technique of Dynamic Logic under Temperature and Process Variations," in Proc. AISCON , 2009, pp. 1236-1239.
  7. G. Yang, Z. Wang, and S. M. Kang, "Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies," in Proc. ICVD, 2004, pp. 222-227.
  8. P. Arun, S. Ramasamy ,"A Low-Power Dual Threshold Voltage Voltage Scaling Technique for Domino Logic Circuits," in Proc. ICCCNT, 2012, pp. 1-6.
  9. S. H. Kim ,V. J. Mooney ,"Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design," in Proc . VLSISOC, 2006, pp. 367-372.
  10. S. J. Shieh, J. S. Wang and Y. H. Yeh ,"A contention-alleviated static keeper for high-performance domino logic circuits," in Proc. ICECS ,2001, pp. 707-710.
  11. H. Upadhyay, A. Choubey, K. Nigam "Comparison Among Different Cmos Inverter With Stack Keeper Approach in VLSI design," IJERA , Vol. 2, Issue 3, May-Jun 2012, pp. 640-646. .
  12. H. Kanno, T. Saeki, H. Abiko, A. Kubo, and K. Tokashiki,"A Voltage-Regulated static Keeper Technique for high-performance ASICs," in Proc. ASIC conference ,1998,pp. 361-368.
Index Terms

Computer Science
Information Sciences

Keywords

Domino logic dual threshold voltage voltage Scaling.