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Super-Fast Low Power (SFLP) SRAM Cell for Read/Write Operation
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 76 - Number 5 |
| Year of Publication: 2013 |
| Authors: C. M. R. Prabhu, Ajay Kumar Singh |
10.5120/13240-0681
|
C. M. R. Prabhu, Ajay Kumar Singh . Super-Fast Low Power (SFLP) SRAM Cell for Read/Write Operation. International Journal of Computer Applications. 76, 5 ( August 2013), 1-5. DOI=10.5120/13240-0681
Abstract
In this paper a Super-Fast Low-Power (SFLP) static random access memory (SRAM) cell has been proposed. The SFLP cell contains two tail transistors in the pull-down path of the respective inverter to minimize the write power consumption The cell is simulated in terms of speed, power and read stability. The simulated results show that the read and write power of the proposed cell is reduced up to 38% and 55% at 1. 2 V respectively and cell achieves 2. 2x higher read static noise margin (SNM) compared to the conventional 6T SRAM cell.
References
- N. S. Kim, D. Blaauw, T. Mudge, "Quantitative analysis and opti- mization techniques for on-chip cache leakage power," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 13, no. 10, pp. 1147-1156, Oct. 2005.
- M. Yamaoka, R. Tsuchiya, and T. Kawahara, "SRAM circuit with ex- panded operating margin and reduced stand-by leakage current using Thin-BOX FD-SOI transistors," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2366-2372, Nov. 2006.
- S. Inaba, H. Nagano, K. Miyano, I. Mizuushima, Y. Okayama, T. Nakauchi, K. Ishimaru, and H. Ishiuchi, " Low-power logic circuit and SRAM cell applications with silicon on depletion layer CMOS (SODEL CMOS) technology," IEEE J. Solid-State Circuits, vol. 41, no. 6, pp. 1455-1462, June 2006.
- A. Chandrakasan, W. J. Bowbill and F. Fox, "Design of High Perfor- mance Microprocessor Circuits," Wiley-IEEE Press, p. 584, 2000.
- E. Grossar, M. Stucchi, K. Maex, and W. Dehaene, "Read stability and write-ability analysis of SRAM cells for nanometer technologies," IEEE J. Solid-State Circuits, vol. 41, no. 11, pp. 2577-2588, Nov. 2006.
- Y. Chang, F. Lai, and C. Yang, "Zero-aware asymmetric SRAM cell for reducing cache power in writing zero," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 12, no. 8, pp. 827-836, Aug. 2004.
- C. M. R. Prabhu and A. K. Singh, Novel Eight-Transistor SRAM cell for Write Power reduction," IEICE Electron. Express, vol. 7, no. 16, pp. 1175-1181, 2010.
- Z. Liu and V. Kursun, "Characterization of a Novel Nine-Transistor SRAM cell," IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol. 16, no. 4, pp. 488-492, Aug. 2008.
- A. Sil, S. Ghosh, and M. Bayoumi, "A Novel 8T SRAM Cell with improved Read-SNM," Circuits and Systems, 2007, NEWCAS 2007. IEEE Northeast Workshop, vol. 5-8, pp 1289-1292, Aug. 2007.
- E. Sicard, "Microwind and Dsch version 3. 0," Published by INSA Toulouse France, April 2005. [online] Available: http://www. microwind. org.
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