The week's pick
Reseach Article
Implementation of Encoder for (31,k) Binary BCH Code based on FPGA for Multiple Error Correction Control
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 76 - Number 11 |
| Year of Publication: 2013 |
| Authors: Samir Jasim Mohammed |
10.5120/13291-0815
|
Samir Jasim Mohammed . Implementation of Encoder for (31,k) Binary BCH Code based on FPGA for Multiple Error Correction Control. International Journal of Computer Applications. 76, 11 ( August 2013), 23-28. DOI=10.5120/13291-0815
Abstract
This paper describes the design and implementation of (31,k) binary BCH (Bose, Chaudhuri, and Hocquenghem) encoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. BCH code is one of the most important cyclic block codes. Designing on FPGA leads to a high calculation rate using parallelization (implementation is very fast), and it is easy to modify. BCH encoder has been designed and simulated using Xilinx-ISE 10. 1 Web PACK and implemented in a xc3s700a-4fg484 FPGA. In this implementation, A 31 bit-size code word has been used. The BCH code encoders of (31, 26, 1), (31, 21, 2), (31, 16, 3), (31, 11, 5) and (31, 6, 7) have implemented on FPGA. The results show that the systems work quite well.
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