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Reseach Article

Implementation of Encoder for (31,k) Binary BCH Code based on FPGA for Multiple Error Correction Control

by Samir Jasim Mohammed
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 76 - Number 11
Year of Publication: 2013
Authors: Samir Jasim Mohammed
10.5120/13291-0815

Samir Jasim Mohammed . Implementation of Encoder for (31,k) Binary BCH Code based on FPGA for Multiple Error Correction Control. International Journal of Computer Applications. 76, 11 ( August 2013), 23-28. DOI=10.5120/13291-0815

@article{ 10.5120/13291-0815,
author = { Samir Jasim Mohammed },
title = { Implementation of Encoder for (31,k) Binary BCH Code based on FPGA for Multiple Error Correction Control },
journal = { International Journal of Computer Applications },
issue_date = { August 2013 },
volume = { 76 },
number = { 11 },
month = { August },
year = { 2013 },
issn = { 0975-8887 },
pages = { 23-28 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume76/number11/13291-0815/ },
doi = { 10.5120/13291-0815 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:45:53.982962+05:30
%A Samir Jasim Mohammed
%T Implementation of Encoder for (31,k) Binary BCH Code based on FPGA for Multiple Error Correction Control
%J International Journal of Computer Applications
%@ 0975-8887
%V 76
%N 11
%P 23-28
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper describes the design and implementation of (31,k) binary BCH (Bose, Chaudhuri, and Hocquenghem) encoder using a Field Programmable Gate Array (FPGA) reconfigurable chip. BCH code is one of the most important cyclic block codes. Designing on FPGA leads to a high calculation rate using parallelization (implementation is very fast), and it is easy to modify. BCH encoder has been designed and simulated using Xilinx-ISE 10. 1 Web PACK and implemented in a xc3s700a-4fg484 FPGA. In this implementation, A 31 bit-size code word has been used. The BCH code encoders of (31, 26, 1), (31, 21, 2), (31, 16, 3), (31, 11, 5) and (31, 6, 7) have implemented on FPGA. The results show that the systems work quite well.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Error correcting codes BCH codes BCH encoder FPGA