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Comparative Analysis of Low Power 10T and 14T Full Adder using Double Gate MOSFET at 45nm Technology

by Anuj Kumar Shrivastava, Shyam Akashe
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 75 - Number 3
Year of Publication: 2013
Authors: Anuj Kumar Shrivastava, Shyam Akashe
10.5120/13095-0378

Anuj Kumar Shrivastava, Shyam Akashe . Comparative Analysis of Low Power 10T and 14T Full Adder using Double Gate MOSFET at 45nm Technology. International Journal of Computer Applications. 75, 3 ( August 2013), 48-52. DOI=10.5120/13095-0378

@article{ 10.5120/13095-0378,
author = { Anuj Kumar Shrivastava, Shyam Akashe },
title = { Comparative Analysis of Low Power 10T and 14T Full Adder using Double Gate MOSFET at 45nm Technology },
journal = { International Journal of Computer Applications },
issue_date = { August 2013 },
volume = { 75 },
number = { 3 },
month = { August },
year = { 2013 },
issn = { 0975-8887 },
pages = { 48-52 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume75/number3/13095-0378/ },
doi = { 10.5120/13095-0378 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:43:20.096163+05:30
%A Anuj Kumar Shrivastava
%A Shyam Akashe
%T Comparative Analysis of Low Power 10T and 14T Full Adder using Double Gate MOSFET at 45nm Technology
%J International Journal of Computer Applications
%@ 0975-8887
%V 75
%N 3
%P 48-52
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Full adder is the basic block of arithmetic circuit found in microcontroller and microprocessor inside arithmetic and logic unit (ALU). Improving the performance of the adder is essential for upgrade the performance of digital electronics circuit where adder is employed. This paper described a comparative analysis of double gate 10T and double gate 14T adder at 45nm technology. In this paper we calculate the leakage current, average power and Delay of the designed circuit of 10T and 14T Full adder. 10T double gate full adder achieves 31. 25% reduction in active power and 95% reduction in leakage current as compared to 14T double gate full adder. Simulation results of double gate full adder have been performed on cadence virtuoso tool with 45nm technology.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Full adder Low power arithmetic operation Double gate mosfet leakage current

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