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Reseach Article
Design of 32-bit Carry Select Adder with Reduced Area
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 75 - Number 2 |
| Year of Publication: 2013 |
| Authors: Yamini Devi Ykuntam, M. V. Nageswara Rao, G. R. Locharla |
10.5120/13086-0353
|
Yamini Devi Ykuntam, M. V. Nageswara Rao, G. R. Locharla . Design of 32-bit Carry Select Adder with Reduced Area. International Journal of Computer Applications. 75, 2 ( August 2013), 47-52. DOI=10.5120/13086-0353
Abstract
Addition is the heart of arithmetic unit and the arithmetic unit is often the work horse of a computational circuit. So adders play a key role in designing an arithmetic unit and also many digital integrated circuits. Carry Select Adder (CSLA) is one of the fastest adders used in many data processors and in digital circuits to perform arithmetic operations. But CSLA is area-consuming because it consists of dual ripple carry adder (RCA) in the structure. To reduce the area of CSLA, a CSLA with Binary to Excess-1 Converter is already designed which reduces the area of adder. But there are other techniques to design a CSLA to reduce its area. One of such technique is using an add one circuit technique. This paper proposes the design of square root CSLA (SQRT CSLA) using add one circuit with significant reduction in area. The proposed design is synthesized using Leonardo Spectrum to get area (number of gates) and delay (ns). The performance in terms of area and delay are evaluated for square root CSLA using add one circuit and are compared with existing SQRT CSLA and SQRT CSLA using Binary to Excess-1 Converter (BEC). The results analysis shows that the proposed SQRT CSLA using add one circuit is better than the existing SQRT CSLA and SQRT CSLA using BEC.
References
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