CFP last date
20 December 2024
Call for Paper
January Edition
IJCA solicits high quality original research papers for the upcoming January edition of the journal. The last date of research paper submission is 20 December 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

High Speed and High Resolution Self Biased Differential Amplifier based Latch Comparator

by Shyam Singh, Ravi Kumar, K. S. Paraliya
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 74 - Number 3
Year of Publication: 2013
Authors: Shyam Singh, Ravi Kumar, K. S. Paraliya
10.5120/12863-9653

Shyam Singh, Ravi Kumar, K. S. Paraliya . High Speed and High Resolution Self Biased Differential Amplifier based Latch Comparator. International Journal of Computer Applications. 74, 3 ( July 2013), 9-13. DOI=10.5120/12863-9653

@article{ 10.5120/12863-9653,
author = { Shyam Singh, Ravi Kumar, K. S. Paraliya },
title = { High Speed and High Resolution Self Biased Differential Amplifier based Latch Comparator },
journal = { International Journal of Computer Applications },
issue_date = { July 2013 },
volume = { 74 },
number = { 3 },
month = { July },
year = { 2013 },
issn = { 0975-8887 },
pages = { 9-13 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume74/number3/12863-9653/ },
doi = { 10.5120/12863-9653 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:41:13.937839+05:30
%A Shyam Singh
%A Ravi Kumar
%A K. S. Paraliya
%T High Speed and High Resolution Self Biased Differential Amplifier based Latch Comparator
%J International Journal of Computer Applications
%@ 0975-8887
%V 74
%N 3
%P 9-13
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In high speed ADC, comparator influences the overall performance of ADC directly. This paper describes a very high speed and high resolution preamplifier comparator. The comparator use a self biased differential amp to increase the output current sinking and sourcing capability. The threshold and width of the new comparator can be reduced to the millivolt (mV) range, the resolution and the dynamic characteristics are good. Based on UMC 0. 18um CMOS process model, simulated results show the comparator can work under a 25dB gain, 55MHz speed and 210. 10µW power .

References
  1. Yavuz De?gerli, Nicolas Fourches, Michel Rouger, and Pierre Lutz, "Low-Power Autozeroed High-Speed Comparator for the Readout Chain of a CMOS Monolithic Active Pixel Sensor Based Vertex Detector", IEEE Transactions on nuclear science , vol. 50, no. 5, pp. 0018-9499, Oct. 2003.
  2. Tursi,Ols Hidri,Valerie Pons, "A 1. 8-V 1. 6-GSample/s 8-b Self-Calibrating Folding ADC With 7. 26 ENOB at Nyquist Frequency", IEEE JOURNAL OF SOLID-STATE CIRCUITS Robert C. Taft, Chris A. Menkus, Maria Rosaria, VOL. 39, NO. 12, DECEMBER 2004, pp. 2107-2115
  3. Carlos J Solis, Gladys O. Ducoudray, "High Resolution Low Power 0. 6?m CMOS 40MHz Dynamic Latch Comparator", IEEE Transactions on, vol. 978, no. 1, pp. 4244-7773, Sept. 2010
  4. Krishnaswamy Nagaraj, David A. Martin, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan, "A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0. 25- _m Digital CMOS Process", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000, pp. 1760-1768.
  5. K. Uyttenhove, and M. S. J. Steyaert, "A 1. 8-V 6-bit 1. 3-GHz flash ADC in 0. 25-um CMOS", IEEE Journal of Solid State Circuits, Volume 45, Issue 11, Page(s):1433 - 1444 Nov. 1998.
  6. Al-Rawi, G. A. ; , "A new offset measurement and cancellation technique for dynamic latches," Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on , vol. 5, no. , pp. V-149- V-152 vol. 5, 2002
  7. Robert C. Taft, Chris A. Menkus, Maria Rosaria Tursi,Ols Hidri, Valerie Pons, "A 1. 8-V 1. 6-GSample/s 8-b Self-Calibrating Folding ADC With 7. 26 ENOB at Nyquist Frequency", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004, pp. 2107-2115.
  8. Krishnaswamy Nagaraj, David A. Martin, Ranjan Chattopadhyay, Shanthi Pavan, Jason Cancio, T. R. Viswanathan, "A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0. 25-_m Digital CMOS Process", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 12, DECEMBER 2000, pp. 1760-1768.
  9. P. M. Figueiredo, and J. C. Vital, "Low kickback noise techniques for CMOS latched comparators", ISCAS '04. Proceedings of the 2004 International Symposium on Circuits and Systems, Volume 1, pp- 537-40 Vol. 1, 23- 26 May 2004.
  10. Marcel J. M. Pelgrom AAD C. J. Dunma- IJER, Anton P. G Welbers, "Matching Properties of MOS Transistors", IEEE Journal of Solid- State Circuits, VOL. 24, NO. 5, October 1989, pp. 1433-1440.
  11. Kotani, K. ; Shibata, T. ; Ohmi, T. ; , "CMOS charge-transfer preamplifier for offset-fluctuation cancellation in low-power A/D converters," Solid-State Circuits, IEEE Journal of , vol. 33, no. 5,pp. 762-769, May 1998.
  12. B. Razavi and B. A. Wooley, "Design Techniques for High-Speed High-Resolution Comparators," IEEE J. Solid-State Circuits, vol. SC-27, pp. 1916-1926, Dec 1992.
  13. N. Stefanou and S. R. Sonkusale, "An average low offset comparator for 1. 25G samples/s ADC in 0. 18 um CMOS", IEEE ECAS.
  14. H. P. Le, A. Zayegh, and J. Singh, "Performance analysis of optimised CMOS comparator," Electronics Letters, vol. 39, pp. 833-835, May 2003.
  15. S. Sheikhaei, S. Mirabbasi, and A. Ivanov, "A 0. 35?m CMOS Comparator Circuit for High-Speed ADC Applications," IEEE International Symposium on Circuits and Systems, pp. 6134-6137, May 2005.
  16. M. Min, P. Kim, F. W. Bowman, D. M. Boisvert, A. J. Aude, "A 69- mW 10-bit 80-MSample/s Pipelined CMOS ADC," IEEE JSSC, vol. 38, pp. 2031-2039, Dec. 2003.
  17. T. W. Matthews, P. L. Heedley, "A Simulation Method for Accurately Determining DC and Dynamic Offset in Comparators," IEEE MWSCAS, pp. 1815-1818, Aug. 2005.
Index Terms

Computer Science
Information Sciences

Keywords

High speed ADC high speed comparator high resolution and preamplifier latch comparator

Powered by PhDFocusTM