Quantum-dot Cellular Automata (QCA) offers a new computing paradigm in nanotechnology and is being considered as the future alternative to state-of-the art CMOS designs. The first introduced logic element, the Majority Voter (MV) led to prohibitively large and complex circuits having both uncomplemented and complemented variables. Subsequently many proposals have been made namely AOI and NNI to overcome these shortcomings. In this work we focus on a novel nanostructure (DPNNI) with double polarisation inputs which uses NAND/NOR gates as the basic building blocks, similar to conventional digital logic circuits. Simulation result shows a minimum of 43% to a maximum of 176% reduction in size of circuits with this structure in comparison to that with the AOI and NNI gates. The widespread acceptance of QCA in logic design demands investigation of defect tolerance of QCA circuit elements. Hence the defect tolerance of the proposed structure with respect to misalignment of the cells in the NAND/NOR structure have also been analyzed. Noise margin is an important figure of merit in digital circuits. The Noise Margin of this proposed structure has also been studied and it is shown to exhibit a high impedance state corresponding to a tristated structure. The fault tolerant properties of the proposed universal gate has been evaluated through simulation with QCA Designer.

QCA DPNNI Noise Margin.