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Novel Architecture of High Speed Parallel MAC using Carry Select Adder

by Deepika Setia, Charu Madhu
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 74 - Number 1
Year of Publication: 2013
Authors: Deepika Setia, Charu Madhu
10.5120/12851-9334

Deepika Setia, Charu Madhu . Novel Architecture of High Speed Parallel MAC using Carry Select Adder. International Journal of Computer Applications. 74, 1 ( July 2013), 32-38. DOI=10.5120/12851-9334

@article{ 10.5120/12851-9334,
author = { Deepika Setia, Charu Madhu },
title = { Novel Architecture of High Speed Parallel MAC using Carry Select Adder },
journal = { International Journal of Computer Applications },
issue_date = { July 2013 },
volume = { 74 },
number = { 1 },
month = { July },
year = { 2013 },
issn = { 0975-8887 },
pages = { 32-38 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume74/number1/12851-9334/ },
doi = { 10.5120/12851-9334 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:41:05.935969+05:30
%A Deepika Setia
%A Charu Madhu
%T Novel Architecture of High Speed Parallel MAC using Carry Select Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 74
%N 1
%P 32-38
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper, new hardware architecture of multiplier and accumulator (MAC) for high speed arithmetic was designed. The performance was improved by merging multiplication with accumulation and organize a hybrid type carry save adder (CSA). The proposed CSA tree uses 1's complement based radix-4 and radix-8 modified booth algorithm(MBA). The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to reduce the number of the input bits of the final adder. This MAC add the intermediate results in the form of sum and carry bits instead of the final adder output, which made it possible to optimize the pipeline system to improve the performance. The final addition was carried out by high speed carry select adder (CSLA) with binary to excess convertor using CLA. Based on the theoretical and experimental estimation, we analyzed the results in terms of delay. The design is implemented using VHDL language and simulated using Xilinx ISE10. 1 Simulator.

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Index Terms

Computer Science
Information Sciences

Keywords

Modified Booth algorithm (MBA) Multiplier and Accumulate (MAC) Carry Look Ahead Adder(CLA) Carry Select adder(CSLA)

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