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Implementation of Running Average Background Subtraction Algorithm in FPGA for Image Processing Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 73 - Number 21 |
| Year of Publication: 2013 |
| Authors: S. Susrutha Babu, S. Suparshya Babu, Habibulla Khan, M. Kalpana Chowdary |
10.5120/13022-0259
|
S. Susrutha Babu, S. Suparshya Babu, Habibulla Khan, M. Kalpana Chowdary . Implementation of Running Average Background Subtraction Algorithm in FPGA for Image Processing Applications. International Journal of Computer Applications. 73, 21 ( July 2013), 41-46. DOI=10.5120/13022-0259
Abstract
In this paper a new background subtraction algorithm was developed to detect moving objects from a stable system in which visual surveillance plays a major role. Initially it was implemented in MATLAB. Among all existing algorithms running average algorithm was choosen because of low computational complexity which is the major parameter of time in VLSI. The concept of the background subtraction is to subtract the current image with respect to the reference image and compare it with to the certain threshold values. We propose a new real time background subtraction algorithm which was implemented with verilog hdl in order to detect moving objects accurately. Our method involves three important modules background modelling; adaptive threshold estimation and finally fore ground extraction. Compared to all existing algorithms our method having low power consumption and low resource utilization. Here we have written the core processor Microblaze is designed in VHDL (VHSIC hardware description language), implemented using XILINX ISE 8. 1 Design suite the algorithm is written in system C Language and tested in SPARTAN-3 FPGA kit by interfacing a test circuit with the PC using the RS232 cable. Area and the speed of the algorithm are also evaluated.
References
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