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Advanced Testbench Design using Reusable Verification Component and OVM

by Viney Malik, Rajesh Mehra, Surender Ahlawat
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 73 - Number 15
Year of Publication: 2013
Authors: Viney Malik, Rajesh Mehra, Surender Ahlawat
10.5120/12820-0277

Viney Malik, Rajesh Mehra, Surender Ahlawat . Advanced Testbench Design using Reusable Verification Component and OVM. International Journal of Computer Applications. 73, 15 ( July 2013), 36-40. DOI=10.5120/12820-0277

@article{ 10.5120/12820-0277,
author = { Viney Malik, Rajesh Mehra, Surender Ahlawat },
title = { Advanced Testbench Design using Reusable Verification Component and OVM },
journal = { International Journal of Computer Applications },
issue_date = { July 2013 },
volume = { 73 },
number = { 15 },
month = { July },
year = { 2013 },
issn = { 0975-8887 },
pages = { 36-40 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume73/number15/12820-0277/ },
doi = { 10.5120/12820-0277 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:40:12.526200+05:30
%A Viney Malik
%A Rajesh Mehra
%A Surender Ahlawat
%T Advanced Testbench Design using Reusable Verification Component and OVM
%J International Journal of Computer Applications
%@ 0975-8887
%V 73
%N 15
%P 36-40
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The paper describes the additional proven techniques for creating highly effective testbenches. This paper presents topics that are likely to be used by most test-benches. Samples of the techniques, as well as the underlying concepts, are presented. The paper shows several ways to use VIP with OVM technology and provides the knowledge to customize, modify, and extend the techniques to suit the needs of SoC designers. The basic steps to create a first constrained random testbench with VIP and OVM is also presented. It can be a template to develop more complex and powerful test-benches using other computing methods and features of OVM and VIP.

References
  1. Mark Glasser"Open Verification Methodology Cookbook" 1st edition, Springer, 2009.
  2. "OVM Golden Reference Guide", version2. 0, Doulos, 2008.
  3. Thomas L. Anderson, "Open Verification Methodology: Fulfilling the Promise of System Verilog" Information Quarterly (IQ) Volume 7, Number 1, pp. 52-54, 2008.
  4. Bryan Ramirez, Michael Horn "Parameters and OVM - Can't They Just Get Along?" Proceedings of Design and Verification Conference & Exhibition (DVCon '11), 2011.
  5. Stephen D'Onofrio, Ning Guo "Building reusable verification environments with OVM" proceedings of EDA Tech Design Forum - 08, pp. 1-9, 2008.
  6. A. Wakefield, B. J. Mohd, "Constructing Reusable Testbenches" Proceedings of the IEEE Conference, High-Level Design Validation and Test Workshop, pp. 151-155, 2002.
  7. Mikhail Chupilko, A. Kamkin, "A TLM-Based Approach to Functional Verification of Hardware Components at Different Abstraction Levels" Proceedings of the IEEE Conference, Test Workshop (LATW), pp. 1-6, 2011.
  8. L. Cai, D. Gajski, "Transaction Level Modeling: an Overview" First International IEEE Conference on Hardware/Software Co-design and System Synthesis (CODESS '03), pp. 19-24, 2003.
  9. Chris Spares "System Verilog for verification" 2nd edition Springer 2008.
  10. Rudra Mukherjee, Sachin Kakkar "Towards an Object-Oriented Design Methodology using SystemVerilog" Proceedings of Design and Verification Conference & Exhibition (DVCon '09), pp. 234-239, 2009
  11. "IEEE Standard for System Verilog—IEEE std. 1800-2009"
  12. "System Verilog Testbench Constructs" www. testbench. in
Index Terms

Computer Science
Information Sciences

Keywords

Open Verification Methodology Verification Intellectual Property System on Chip Design Under Test Transaction Level Modeling

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