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An AES-based Intellectual-Property Identification in System-on-a-Chip Design

by P. G. Gopinath, K. Adithya, B. Ajay
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 72 - Number 9
Year of Publication: 2013
Authors: P. G. Gopinath, K. Adithya, B. Ajay
10.5120/12523-9034

P. G. Gopinath, K. Adithya, B. Ajay . An AES-based Intellectual-Property Identification in System-on-a-Chip Design. International Journal of Computer Applications. 72, 9 ( June 2013), 28-33. DOI=10.5120/12523-9034

@article{ 10.5120/12523-9034,
author = { P. G. Gopinath, K. Adithya, B. Ajay },
title = { An AES-based Intellectual-Property Identification in System-on-a-Chip Design },
journal = { International Journal of Computer Applications },
issue_date = { June 2013 },
volume = { 72 },
number = { 9 },
month = { June },
year = { 2013 },
issn = { 0975-8887 },
pages = { 28-33 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume72/number9/12523-9034/ },
doi = { 10.5120/12523-9034 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:37:29.360676+05:30
%A P. G. Gopinath
%A K. Adithya
%A B. Ajay
%T An AES-based Intellectual-Property Identification in System-on-a-Chip Design
%J International Journal of Computer Applications
%@ 0975-8887
%V 72
%N 9
%P 28-33
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper presents a novel intellectual-property (IP) identification scheme using the existing System-on-a-Chip (SOC) watermarking design. An efficient and novel principle is established for IP identification which depends on the current IP design flow. The principle is embedding different Advanced Encryption Standard (AES) encoders in to System-on-a-Chip (SOC) based watermarked devices at behavior design level. Here the AES encoders provide additional security to the previously generated watermark sequences. This method is efficient as it survives synthesis, placement, and routing and can identify the IP at various levels. It may be easy to detect the identification of the provider even after the chip has been manufactured. The proposed method increases security for the System-on-a-Chip (SOC) based IP identification and protection scheme.

References
  1. H. Chang, Surviving the SOC Revolution: A Guide to Platform-Based Design. Norwell, MA: Kluwer, 1999.
  2. G. Martin and H. Chang, Winning the SoC Revolution: Experiences in Real Design. Norwell, MA: Kluwer, 2003.
  3. I. J. Cox, M. L. Miller, and J. A. Bloom, Digital Watermarking. San Mateo, CA: Morgan Kaufmann, 2002.
  4. I. J. Cox, J. Kilian, F. T. Leighton, and T. Shamoon, "Secure spread spectrum watermarking for multimedia," IEEE Trans. Image Process. , vol. 6, no. 12, pp. 1673–1687, Dec. 1997.
  5. Y. P. Wang, M. J. Chen, and P. Y. Cheng, "Robust image watermark with wavelet transform and spread spectrum techniques," in Proc. Asilomar Conf. Signals Syst. , Comput. , Nov. 2000, vol. 2, pp. 1846–1850.
  6. Q. Sun and S. F. Chang, "Semi-fragile image authentication using generic wavelet domain features and ECC," in Proc. Int. Conf. Image Process. , Sep. 2002, vol. 2, pp. , 901–904.
  7. Y. L. Ho and H. C. Wang, "An audio watermarking algorithm based on significant component modulation," in Proc. IEEE Int. Conf. Consum. Electron. , Jun. 2003, pp. 212–213.
  8. T. H. Tsai and C. Y. Wu, "An implementation of configurable digital watermarking system in MPEG video encoder," in Proc. IEEE Int. Conf. Consum. Electron. , Jun. 2003, pp. 216–217.
  9. A. B. Kahng, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang,and G. Wolfe, "Robust IP watermarking methodologies for physical design,"in Proc. IEEE Des. Autom. Conf. , Jun. 1998, pp. 782–787.
  10. A. B. Kahng et al. , "Constraint-based watermarking techniques for design IP protection," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst. , vol. 20, no. 10, pp. 1236–1252, Oct. 2001.
  11. A. B. Kahng, D. Kirovski, S. Mantik, M. Potkonjak, and J. L. Wong, "Copy detection for intellectual property protection of VLSI designs," in Proc. IEEE/ACM Int. Conf. Comput. -Aided Des. , 1999, pp. 600–604.
  12. N. Narayan, R. D. Newbould, J. D. Carothers, J. J. Rodriguez, and W. T. Holman, "IP protection for VLSI designs via watermarking of routes," in Proc. IEEE Int. Conf. ASIC/SOC, Sep. 2001, pp. 406–410.
  13. D. Kirovski and M. Potkonjak, "Localized watermarking: Methodology and application to template mapping," in Proc. IEEE Int. Conf. Acoust. , Speech, Signal Process. , Jun. 2000, vol. 6, pp. 3235–3238.
  14. A. E. Caldwell, H. J. Choi, A. B. Kahng, S. Mantik, M. Potkonjak, G. Qu, and J. L. Wong, "Effective iterative techniques for fingerprinting design IP," in Proc. Des. Autom. Conf. , Jun. 1999, pp. 843–848.
  15. J. Lach, W. H. Mangione-Smith, and M. Potkonjak, "Fingerprinting digital circuits on programmable hardware," in Proc. Int. Workshop Inf. Hiding, 1998, pp. 16–31.
  16. E. Charbon, "Hierarchical watermarking in IC design," in Proc. IEEE Custom Integr. Circuits Conf. , May 1998, pp. 295–298.
  17. G. Wolfe, J. L. Wong, and M. Potkonjak, "Watermarking graph partitioning solutions," IEEE Trans. Comput. - Aided Design Integr. Circuits Syst. , vol. 21, no. 10, pp. 1196–1204, Oct. 2002.
  18. A. B. Kahng, J. Lach, W. H. Mangione-Smith, S. Mantik, I. L. Markov, M. Potkonjak, P. Tucker, H. Wang, and G. Wolfe,"Watermarking techniques for intellectual property protection," in Proc. IEEE Des. Autom. Conf. , 1998, pp. 776-781.
  19. L. Oliveira, "Techniques for the creation of digital watermarks in sequential circuit designs," IEEE Trans. Comput. -Aided Design Integr. Circuits Syst. , vol. 20, no. 9, pp. 1101–1117, Sep. 2001.
  20. I. Torunoglu and E. Charbon, "Watermarking-based copyright protection of sequential functions," in Proc. IEEE Custom Integr. Circuits Conf. , 1999, pp. 35–38.
  21. R. Chapman and T. S. Durrani, "IP protection of DSP algorithms for system on chip implementation," IEEE Trans. Signal Process. , vol. 48, no. 3, pp. 854–861, Mar. 2000.
  22. R. Chapman, T. S. Durrani, and A. P. Tarbert, "Watermarking DSP algorithms for system on chip implementation," in Proc. IEEE Int. Conf. Electron. , Circuits Syst. , 1999, pp. 377–380.
  23. A. T. Abdel-Hamid, S. Tahar, and E. M. Aboulhamid, "IP watermarking techniques: Survey and comparison," in Proc. IEEE Int. Workshop System-on-Chip Real-Time Appl. , 2003, pp. 60–65.
  24. Yu-Cheng Fan, "Testing-Based Watermarking Techniques for Intellectual-Property Identification in SOC Design," IEEE Trans. Instrumentation AND measurements, vol. 57, no. 3, march 2008
  25. Joan Daemen, Vincent Rijmen,"AES Proposal: Rijndael".
  26. Ross Anderson, Eil Biham, Lars Knuden," Serpent: A Flexible Block Cipher With Maximum Assurance".
  27. Bruce Schneier_ John Kelseyy Doug Whitingz David Wagnerx Chris Hall Niels Ferguson, "TwoFish: A 128- Bit Block Cipher"
  28. Ronald L. Rivest, M. J. B. Robshaw, R. Sidney, and Y. L. Yin,"The RC6 Block Cipher".
  29. C Burwick, D Coppersmith, E D'Avignon, R Gennaro, S Halevi, C Jutla, S M Matyas, L O'Connor, M Peyravian, D Safford et al. "The Mars Encryption Algorithm".
Index Terms

Computer Science
Information Sciences

Keywords

Intellectual-Property (IP) identification system-on-a-chip (SOC) very large scale integration (VLSI) design watermarking Advanced Encryption Standard (AES)

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