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Analyzing the Impact of Stacking Power Gating Technique on Ground Bounce Noise Effect of 3-Bit Flash Analog to Digital Converter
by
Swati Mishra,
Shyam Akashe
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 72 - Number 3 |
| Year of Publication: 2013 |
| Authors: Swati Mishra, Shyam Akashe |
10.5120/12477-8875
|
Swati Mishra, Shyam Akashe . Analyzing the Impact of Stacking Power Gating Technique on Ground Bounce Noise Effect of 3-Bit Flash Analog to Digital Converter. International Journal of Computer Applications. 72, 3 ( June 2013), 34-39. DOI=10.5120/12477-8875
@article{
10.5120/12477-8875,
author = {
Swati Mishra,
Shyam Akashe
},
title = { Analyzing the Impact of Stacking Power Gating Technique on Ground Bounce Noise Effect of 3-Bit Flash Analog to Digital Converter },
journal = {
International Journal of Computer Applications
},
issue_date = { June 2013 },
volume = { 72 },
number = { 3 },
month = { June },
year = { 2013 },
issn = { 0975-8887 },
pages = {
34-39
},
numpages = {9},
url = {
https://ijcaonline.org/archives/volume72/number3/12477-8875/
},
doi = { 10.5120/12477-8875 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:36:58.949480+05:30
%A Swati Mishra
%A Shyam Akashe
%T Analyzing the Impact of Stacking Power Gating Technique on Ground Bounce Noise Effect of 3-Bit Flash Analog to Digital Converter
%J International Journal of Computer Applications
%@ 0975-8887
%V 72
%N 3
%P 34-39
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract
In present scenario high speed and low power devices in signal processing system is generally needed the efficient design and reduced complexity of converters, therefore conventional flash ADC is not fully meet the required specifications. ADC with high speed and low resolution is required in present communication technologies. Lower leakage current with low power consumption is considerable effect for different parameter optimization of flash ADC. The approach for reducing the leakage current is stacking power gating technique in three modes sleep, active and sleep-to-active modes. The design circuit has been simulated using cadence virtuoso tool with 45nm CMOS technology at various supply voltages. Ground bounce noise reduction has been done in flash ADC with stacking power gating approach to reduce the leakage current and active power.
References
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Index Terms
Computer Science
Information Sciences
Keywords