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Low Leakage Multi Threshold Level Shifter Design using Sleepy Keeper
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 72 - Number 22 |
| Year of Publication: 2013 |
| Authors: Shanky Goyal, Vemu Sulochana |
10.5120/12671-9038
|
Shanky Goyal, Vemu Sulochana . Low Leakage Multi Threshold Level Shifter Design using Sleepy Keeper. International Journal of Computer Applications. 72, 22 ( June 2013), 1-6. DOI=10.5120/12671-9038
Abstract
In this paper, a low leakage multi Vth level shifter is designed for robust voltage shifting from sub threshold to above threshold domain using MTCMOS technique and sleepy keeper. Multi Threshold CMOS is an effective circuit level technique that improves the performance and design by utilizing both low and high threshold voltage transistors. Power dissipation has become an overriding concern for VLSI circuit designers. In this a "sleepy keeper" approach is preferred which reduces the leakage current while saving exact logic state. New low-power level shifter using sleepy keeper is compared with the previous work for different values of the lower supply voltage. The circuits are individually analyzed for power consumption at 45nm CMOS technology, new level shifter offer significant power savings up to 37% as compared to the previous work. On the other hand, when the circuits are individually analyzed for minimum propagation delay, speed is enhanced by up to 48% with our approach to the circuit. All these simulation results are based on 45nm CMOS technology and simulated in cadence tool.
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