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Characterization of 6T SRAM Cell DRV for ULP Applications

by Sanjay Kr Singh, D. S. Chauhan, B. K. Kaushik, Vaibhav Dipankar, Navneet Kr. Chaurasia
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 72 - Number 20
Year of Publication: 2013
Authors: Sanjay Kr Singh, D. S. Chauhan, B. K. Kaushik, Vaibhav Dipankar, Navneet Kr. Chaurasia
10.5120/12659-9354

Sanjay Kr Singh, D. S. Chauhan, B. K. Kaushik, Vaibhav Dipankar, Navneet Kr. Chaurasia . Characterization of 6T SRAM Cell DRV for ULP Applications. International Journal of Computer Applications. 72, 20 ( June 2013), 27-33. DOI=10.5120/12659-9354

@article{ 10.5120/12659-9354,
author = { Sanjay Kr Singh, D. S. Chauhan, B. K. Kaushik, Vaibhav Dipankar, Navneet Kr. Chaurasia },
title = { Characterization of 6T SRAM Cell DRV for ULP Applications },
journal = { International Journal of Computer Applications },
issue_date = { June 2013 },
volume = { 72 },
number = { 20 },
month = { June },
year = { 2013 },
issn = { 0975-8887 },
pages = { 27-33 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume72/number20/12659-9354/ },
doi = { 10.5120/12659-9354 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:38:26.865197+05:30
%A Sanjay Kr Singh
%A D. S. Chauhan
%A B. K. Kaushik
%A Vaibhav Dipankar
%A Navneet Kr. Chaurasia
%T Characterization of 6T SRAM Cell DRV for ULP Applications
%J International Journal of Computer Applications
%@ 0975-8887
%V 72
%N 20
%P 27-33
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

This paper examines the characteristics of 6T SRAM Cell Data Retention Voltage (DRV). It also presents different DRV minimization techniques for ULP applications. The 6T SRAM cell is designed in 180nm CMOS technology. The cell is simulated to by varying different DRV dependent parameters to understand the effects on it.

References
  1. Huifang Qin, Yu Cao, Dejan Markovic, Andrei Vladimirescu, Jan Rabaey, Standby supply voltage minimization for deep sub-micron SRAM, Microelectronics Journal 36 (2005) 789-800
  2. S. Kumar V, A. Noor, Characterization and Comparison of low power SRAM cells, journal of electron Devices, Vol. 11 2011, pp. 560-566.
  3. B. Cheng, S. Roy, A. Asenov, CMOS 6T SRAM cell design subject to "atomistic" fluctuations, Solid-State Electronics 51 (2007) 565-571.
  4. Christiensen D. C. Arandilla, Anastacia B. Alvarez, and Christian Raymund K. Roque, Static Noise Margin of 6T SRAM Cell in 90-nm CMOS, 2011 UKSim 13th International Conference on Modelling and Simulation, IEEE Computer Society.
  5. Animesh Kumar, Huifang Qin, Prakash Ishwar†, Jan Rabaey, and Kannan Ramchandran, Fundamental Data Retention Limits in SRAM Standby – Experimental Results, 9th International Symposium on Quality Electronic Design, 2008
  6. A. Kumar, H. Qin, P. Ishwar, J. Rabaey and K. Ramachandran, Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAM, IEEE, 2007
  7. Sanjay Kr Singh, Sampath Kumar, Arti Noor, D. S. Chauhan & B. K. Kaushik, Deep Sub-Micron SRAM design for DRV analysis and low leakage, International Journal of Advances in Engineering & Technology, 2011.
  8. Sampath Kumar, Sanjay Kr Singh, Arti Noor and B. K. Kaushik, Deep Sub-Micron SRAM Design for Low Leakage, Int'l Conf. on Computer & Communication Technology, 2010
Index Terms

Computer Science
Information Sciences

Keywords

CMOS SNM DRV CR PR

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