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Systematic Approach in Building Clock Tree for SOC’s
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 72 - Number 15 |
| Year of Publication: 2013 |
| Authors: Viswanath Reddy K, S. Jagannathan |
10.5120/12572-9189
|
Viswanath Reddy K, S. Jagannathan . Systematic Approach in Building Clock Tree for SOC’s. International Journal of Computer Applications. 72, 15 ( June 2013), 24-26. DOI=10.5120/12572-9189
Abstract
The biggest problem we faced in designing clock trees is skew minimization. The reasons that add to clock skew include loading mismatch at the clocked elements, mismatch in RC delay. In the present scenario, if we set target insertion delay to the tool then minimum insertion delay is target and maximum insertion delay is floating i. e. , global skew is not constant. This is undesirable so we achieve the control on insertion delay by performing many experiments on different parameters like target insertion delay, Global skew, clock shielding, Inserting redundant vias and Non-Default Routing rules (NDR). So far, we achieved 11. 76% and 1. 7% reduction in global skew and target insertion delay without clock shielding. But this is going to effect crosstalk even worse. So, with the help of NDR rules, we achieved 25. 29% and 3. 675% reduction in global skew and target insertion delay respectively. This project was done with the help of IC-compiler tool from synopsys. This deals with the controlling of Insertion delay and framing systematic approach in building clock tree for SOC's.
References
- R. Rajsuman, System-on-a-Chip: Design and Test. Boston, MA: Artech House Publishers, 2000.
- http://www. docin. com/p-51028067. html, SNUG, 2007
- Anand Rajaram and David Z. Pan, "Robust chip level clock tree synthesis" IEEE Transactions On Computer-Aided Design Of Integrated Circuits And Systems, vol. 30, no. 6, June 2011
- http://www. academia. edu/268923/A_Novel_Approach_to_Reduce_Delay_and_Power_In_VLSI_Interconnects, sandeepsaini, may 2010.
- HimanshuBhatnagar, "Advanced ASIC Chip Synthesis", 2nd Edition Kluwer Academic Publishers, Springer 2002
- "IC Compiler Implementation User Guide" version E-2010. 12-SP2, March 2011.
- "Synopsys Timing Constraints and Optimization User Guide" version D-2010. 03, March 2010.
- "Schmitt Trigger is an alternative to buffer insertion for delay and power reduction in VLSI interconnects" TECTON 2009-2009 IEEE Region 10 conference.
- GolshanKhosrow, "physical Design Essentials: An ASIC Design Implementation perspective", Springer 2007.
- Sabih H. Gerez, "Algorithms For VLSI Design Automation", John Wiley and Sons, 2nd Edition 2009.
- "Clock Tree Synthesis under Aggressive buffer Insertion", ying-yu chen, chen Dong, ICIMS 2010.
- Zhang, and E. G. Friedman, "Crosstalk modeling for coupled RLC interconnect with application to shield insertion," IEEE Trans. VLSI, vol. 14, no. 6, June 2006, pp. 641-646.
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