The biggest problem we faced in designing clock trees is skew minimization. The reasons that add to clock skew include loading mismatch at the clocked elements, mismatch in RC delay. In the present scenario, if we set target insertion delay to the tool then minimum insertion delay is target and maximum insertion delay is floating i. e. , global skew is not constant. This is undesirable so we achieve the control on insertion delay by performing many experiments on different parameters like target insertion delay, Global skew, clock shielding, Inserting redundant vias and Non-Default Routing rules (NDR). So far, we achieved 11. 76% and 1. 7% reduction in global skew and target insertion delay without clock shielding. But this is going to effect crosstalk even worse. So, with the help of NDR rules, we achieved 25. 29% and 3. 675% reduction in global skew and target insertion delay respectively. This project was done with the help of IC-compiler tool from synopsys. This deals with the controlling of Insertion delay and framing systematic approach in building clock tree for SOC's.

Insertion delay Global skew clock shielding NDR rules