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Delay Minimization in Multi Level Balanced Interconnect Tree
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 72 - Number 11 |
| Year of Publication: 2013 |
| Authors: Shwetambhri Kaushal, Vemu Sulochan |
10.5120/12536-9023
|
Shwetambhri Kaushal, Vemu Sulochan . Delay Minimization in Multi Level Balanced Interconnect Tree. International Journal of Computer Applications. 72, 11 ( June 2013), 7-11. DOI=10.5120/12536-9023
Abstract
This paper presents an effective approach to estimate tree interconnect delays in VLSI circuit designs in deep submicron technologies at high frequencies. In this paper, a symmetrical multi-level interconnect tree network topology has been taken up which consists of elementary resistance, inductance in series with capacitance in parallel. A precise method of modeling symmetrical T-tree interconnect network is effectively examined in this paper. By moment matching fine results are obtained at frequencies as high as 2 GHz at 180 nm technology node.
References
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