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Performance Enhancement of MISISFET Structure using SOI (Silicon on Insulator)
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 71 - Number 21 |
| Year of Publication: 2013 |
| Authors: Sanjeev Kumar, Gargi Khanna |
10.5120/12612-9317
|
Sanjeev Kumar, Gargi Khanna . Performance Enhancement of MISISFET Structure using SOI (Silicon on Insulator). International Journal of Computer Applications. 71, 21 ( June 2013), 30-32. DOI=10.5120/12612-9317
Abstract
The present paper proposes the SOI-MISISFET (Silicon on insulator-Metal insulator semiconductor insulator semiconductor FET) structure for the leakage current reduction and low power applications. Performance analysis of SOI-MISISFET has been carried out in this paper and the device is compared with that of conventional MOSFET and MISISFET structures. For optimizing the performance of the device in the nanometer regime, we replaced oxide layer of MOSFET, with a 'dielectric stack' as an insulator and further it is integrated with SOI for reduction of substrate leakage current. Analysis is carried out by using T-CAD Sentaurus tool for 45nm technology. It is observed that the proposed transistor not only reduces the off current by factor of two but enhances the on current twice.
References
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