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High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 71 - Number 18 |
| Year of Publication: 2013 |
| Authors: Zared Kamal, Qjidaa Hassan, Zouak Mohcine |
10.5120/12584-9159
|
Zared Kamal, Qjidaa Hassan, Zouak Mohcine . High PSRR Full On-Chip CMOS Low Dropout Voltage Regulator for Wireless Applications. International Journal of Computer Applications. 71, 18 ( June 2013), 7-16. DOI=10.5120/12584-9159
Abstract
This paper presents a high PSRR full on-chip and area efficient low dropout voltage regulator (LDO), exploiting the nested miller compensation technique with active capacitor (NMCAC) to eliminate the external capacitor. A novel technique is used to boost the important characteristic for wireless applications regulators PSRR. The idea is applied to stabilize the Low dropout regulator. The proposed regulator LDO works with a supply voltage as low as 1. 8 V and provides a load current of 50 mA with a dropout voltage of 200 mV. It is designed in 0. 18 µm CMOS technology and the active area on chip measures 241×187 µm2. Simulation results show that the PSR of LDO is -60 dB at a frequency of 60 KHz and -41. 7 dB at a frequency of 1 MHz.
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