The week's pick
Random Articles
Reseach Article
Evaluating FPGA Virtex-II Board using Dynamic Partial Reconfiguration
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 71 - Number 1 |
| Year of Publication: 2013 |
| Authors: Imran Hashmi, Habibullah Jamal, Tahir Muhammad |
10.5120/12326-8559
|
Imran Hashmi, Habibullah Jamal, Tahir Muhammad . Evaluating FPGA Virtex-II Board using Dynamic Partial Reconfiguration. International Journal of Computer Applications. 71, 1 ( June 2013), 40-45. DOI=10.5120/12326-8559
Abstract
The Field Programmable Gate Array (FPGA) offer effective suppleness and performance because of reconfigurable hardware but consume more power in contrast to the Application Specific Integrated Circuit (ASIC). At run time reconfiguration of hardware in FPGAs can not only be very economical but can be real alternative for ASICs. The designers are reluctant to use Dynamic Partial Reconfiguration (DPR) in FPGA due to lack of adequate tools provided by the vendors. DPR has been in academic use for more over a decade. DPR offers reduction in power consumption, area, cost as well as increase in flexibility, efficiency and fault tolerance but has an application dependent overhead. In this work prior performance of DPR is evaluated using Xilinx Virtex II Pro in order to realize whether it is suitable for an application rather than at later complex design stages of a system design having the DPR employed. The evaluation is based on the reconfiguration speed and the resource utilization. The DPR shows an improvement of resource utilization by 22. 5 % (in terms of slices) as well as speedup in comparison to Non-DPR design.
References
- K. Papadimitriou, A. Dollas, and S. Hauk. . 2010. An effective framework to evaluate dynamic partial reconfiguration in FPGA systems. Instrumentation and Measurement, IEEE Transactions.
- Line P. L. D. , 2008. , Xilinx honored for enabling technology in the ALICE experiment at CERN. Xilinx Inc. , San Jose, CA.
- Compton K. and S. Hauck. , 2002. Reconfigurable computing: a survey of systems and software. ACM Computing Surveys
- Press Release, 2006. ISR and Xilinx Roll Out Ready-to-Wear SDR. Xilinx Inc. San Jose. [online] Available www. fpgajouranl. com
- Gholamipour A. H. Hamid E. Ahmed E. and Fadi K. 2009. Size-reconfiguration delay tradeoffs for a class of DSP blocks in multi-mode communication systems. In Field Programmable Custom Computing Machines.
- Paulsson k. Hubner M. and Becker J. 2008. Cost-and power optimized FPGA based system integration: methodologies and integration of a low-power capacity-based measurement application on Xilinx FPGAs. In Design, Automation and Test in Europe.
- McDonald E. J. 2008. Runtime FPGA partial reconfiguration. In IEEE Aerospace Conference.
- Noguera J. and Kennedy I. O 2007. Power reduction in network equipment through adaptive partial reconfiguration. In International Conference on Field Programmable Logic and Applications.
- Hanho L. 2007. A self-reconfigurable adaptive FIR filter system on partial reconfiguration platform. IEICE transactions on information and systems.
- Kao C. 2005. Benefits of partial reconfiguration. Xcell journal.
- Papadimitriou, K. , Dollas A. and Hauck S. 2011 Performance of partial reconfiguration in FPGA systems: A survey and a cost model. ACM Transactions on Reconfigurable Technology and Systems.
- Hsiung P. A. , Lin C. S. , and Liao C. F. , 2008. Perfecto: A systemc-based design-space exploration framework for dynamically reconfigurable architectures. ACM Transactions on Reconfigurable Technology and Systems.
- Griese B. , Erik V. , Mario P. and Ulrich R. , 2004. Hardware support for dynamic reconfiguration in reconfigurable SoC architectures. In Field Programmable Logic and Application.
- Galindo J. , Eric P. , Brad L. and Gene R. , 2008. Leveraging firmware in multichip systems to maximize FPGA resources: An application of self-partial reconfiguration. In international conference on Reconfigurable Computing and FPGAs.
- Choi C. S. and Lee H. , 2006. An reconfigurable FIR filter design on a partial reconfiguration platform. In international conference on Communications and Electronics.
- Paulsson K. , Michael H. , Salih B. and Jurgen B. , 2007. Exploitation of run-time partial reconfiguration for dynamic power management in Xilinx spartan III-based systems. Reconfigurable system on chip Montpellier, France.
- Claus C. , Florian H. M. , Johannes Z. and Walter S. , 2007. A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. In IEEE Parallel and Distributed Processing Symposiu.
- Claus C. , Zhang B. , Stechele W. , Braun L. , Hubner M. and Becker J. , 2008. A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput. In international conference on Field Programmable Logic and Applications.
- Xilinx. Inc. www. xilinx. com/support/documentation/xapp290. pdf [Online].
Index Terms
Keywords