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Analysis of Power Efficient Modulo 2n+1 Adder Architectures
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 70 - Number 4 |
| Year of Publication: 2013 |
| Authors: M.parimaladevi, R.karthi |
10.5120/11948-7765
|
M.parimaladevi, R.karthi . Analysis of Power Efficient Modulo 2n+1 Adder Architectures. International Journal of Computer Applications. 70, 4 ( May 2013), 8-16. DOI=10.5120/11948-7765
Abstract
Two modified architectures for modulo 2n+1 adders are introduced in this paper. Only some of the carries of modulo 2n+1 addition are computed in sparse carry computation unit present in first architecture. This sparse approach is introduced by inverted circular idempotency property of the parallel-prefix carry operator and in this modified pre-processing stage and carry select blocks are combine the multiplexer operation of a diminished-one adder can be implemented in smaller LUT's and less consumes power, while maintain the same operating speed and delay. The modulo adder 2n+1 adders can be easily derived by adding extra logic of modulo 2n-1 adders present in second architecture.
References
- www. cs. kent. edu/~rothstei/modular_arith. ppt
- http://www. cs. odu. edu/~cs772/fall04/lectures /public_key_cryptography. html
- G. Dimtra Kopulous, D. G. Nikolos, D. Nikolos, H. T. Vergos, and C. Efstathiou,' New Architectures for Modulo 2n-1 Adders," proc. IEEE Int'1 Conf. Electronics, Circuits, and Systems, 2008.
- G. Jaberipur and B. parhami," Unified Approach to the Design of Modulo-(2n±1) Adders Based on Signed-LSB Representation of Residues," proc. 19th IEEE symp. Computer Arithmetic, pp. 57-64, 2009.
- R. Zimmerman," Efficient VLSI Implementation of Modulo (2n±1) Addition and Multiplication," proc. 14th IEEE symp. Computer Arithmetic, pp. 158-167, Apr. 1999.
- R. Zimmerman,"Binary Adder Architectures for Cell-Based VLSI and Their Synthesis," PhD dissertation, Swiss Fed. Inst of Technology, 1977.
- H. T. Vergos, C. Efstathiou, and D. Nikolos," Diminished-One Modulo 2n+1 Adder Design," IEEE Trans. Computers, vol. 51, no. 12, pp. 1389-1399, Dec. 2002.
- C. Efstathiou, H. T. Vergos, and D. Nikolos," Modulo 2n±1 Adder Design Using Select Prefix Blocks," IEEE Trans. Computers, vol. 52, no. 11, pp. 1399-1406, nov. 2003.
- S. -H. Lin and M. -H. Sheu," VLSI Design of Diminished-One Modulo 2n+1 Adder Using Circular Carry Selection," IEEE Trans. Circuits and Systems II, vol. 55, no. 9, pp. 897-901, Sept. 2008.
- A. Hissat, "High-Speed and Reduced-Area Modular Adder Structures for RNS," IEEE Trans. Computers, vol. 53, no. 1, pp. 84-89, Jan. 2002.
- C. Efstathiou, H. T. Vergos, and D. Nikolos," Fast Parallel-Prefix Modulo 2n+1 adders," IEEE Trans. Computers, vol. 53, no. 9, pp. 1211-1216, Sept. 2004.
- H. T. Vergos, and C. Efstathiou," A Unifying Approach for Weighted and Diminished-1 Modulo 2n+1 Addition," IEEE Trans. Circuits and Systems II, vol. 55, no. 10, pp. 1041-1045, Oct. 2008.
- L. kalampoukas et al. , "High-speed Parallel-Prefix Modulo 2n-1 Adders," IEEE Trans. Computers, vol. 49, no. 7, pp. 673-680, July 2000.
- R. A. Patel, M. Bonaissa, and S. Boussakta,"Fast Parallel-Prefix Architecture for Modulo 2n-1 Addition with a Single Representation of Zero," IEEE Trans. Computers, vol. 56, no. 11, pp. 1484-1492, Nov. 2007.
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