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128 Bit Low Power and Area Efficient Carry Select Adder
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 69 - Number 6 |
| Year of Publication: 2013 |
| Authors: Sudhanshu Shekhar Pandey, Amit Bakshi, Vikash Sharma |
10.5120/11846-7587
|
Sudhanshu Shekhar Pandey, Amit Bakshi, Vikash Sharma . 128 Bit Low Power and Area Efficient Carry Select Adder. International Journal of Computer Applications. 69, 6 ( May 2013), 29-33. DOI=10.5120/11846-7587
Abstract
Carry Select Adder (CSLA) which provides one of the fastest adding performance. Traditional CSLA require large area and more power. Recently a new CSLA adder has been proposed which performs fast addition, while maintaining low power consumption and less area. This work mainly focuses on implementing the 128 bit low power and area efficient carry select adder using 0. 18 µm CMOS technology. Based on the efficient gate level modification, 128-b Square Scheme Block (SSB) CSLA) architecture have been developed and compared with the regular SSB CSLA architecture. The performance of the proposed SSB CSLA evaluated manually in terms of delay, power, and area manually with logical effort and also through custom design. The proposed design has been developed using verilog HDL and synthesized in cadence RTL compile using typical library of TSMC 0. 18µm technology.
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