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Implementation of DSP System for Discrete Transforms using VHDL

by Deepak Kumar, K. Anusudha
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 69 - Number 26
Year of Publication: 2013
Authors: Deepak Kumar, K. Anusudha
10.5120/12138-8428

Deepak Kumar, K. Anusudha . Implementation of DSP System for Discrete Transforms using VHDL. International Journal of Computer Applications. 69, 26 ( May 2013), 42-45. DOI=10.5120/12138-8428

@article{ 10.5120/12138-8428,
author = { Deepak Kumar, K. Anusudha },
title = { Implementation of DSP System for Discrete Transforms using VHDL },
journal = { International Journal of Computer Applications },
issue_date = { May 2013 },
volume = { 69 },
number = { 26 },
month = { May },
year = { 2013 },
issn = { 0975-8887 },
pages = { 42-45 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume69/number26/12138-8428/ },
doi = { 10.5120/12138-8428 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:31:40.981328+05:30
%A Deepak Kumar
%A K. Anusudha
%T Implementation of DSP System for Discrete Transforms using VHDL
%J International Journal of Computer Applications
%@ 0975-8887
%V 69
%N 26
%P 42-45
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Discrete Cosine transform (DCT), Inverse DCT, Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are performed by DSP system on one platform. This paper represent the design of a Digital Signal Processor (DSP) system described using VHDL and implement in a Field Programmable Logic Array (FPGA). The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the very vital applications of the fast Fourier transform include Signal analysis, Sound filtering, Data compression, Partial differential equations, Multiplication of large integers, Image filtering etc. Fast Fourier transform (FFT) is an efficient implementation of the Discrete Fourier Transform (DFT). This paper concentrates on the development of the Fast Fourier Transform (FFT), based on Decimation-In-Time (DIT) domain, Radix-2 algorithm, this paper uses VHDL as a design entity, and their Synthesis by Xilinx Synthesis Tool. The input of Fast Fourier transform has been given by testbench and output has been displayed using the waveforms on the Xilinx Design Suite 13. 1. The synthesis results show that the computations for calculating the Fast Fourier transform. By using a fixed geometry addressing, pipeline designing and block fixed point structure, the data has the greater precision and dynamic range. The results show that the design is efficient, strongly extensive and occupies less resource. It is a good method to meet the high-speed digital signal processing requirements.

References
  1. Asmita Haveliya "Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation" IEEE 2nd International Conference on Advanced Computing & Communication Technologies, pp. 167-171, Jan. 2012, India.
  2. S. Belkouch, M. El Aakif and A. Ait Ouahman "Improved Implementation of a Modified Discrete Cosine Transform on Low-Cost FPGA" IEEE 5th International Symposium on I/V Communications and Mobile Network, Oct 2010, Rabat, Morocco.
  3. Zi-Wei Zheng and Zhe Ren "Efficient Design of Fast Fourior Transform Processor Using FPGA Technology" IEEE International Conference on Electrical and Control Engineering, pp. 5195-5198, June 2010, Wuhan, China.
  4. LI Xiao-feng, Chen Long, Wang Shihu "The Implementation of High-speed FFT processor based on FPGA" IEEE International Conference on Computer, Mechatronics, Control & Electronic Engineering (CMCE), Vol. 2 pp. 236-239, Aug 2010, Changchun, China.
  5. Jarrod D. Luker and Vinod B. Prasad "RISC System Design in an FPGA" IEEE Conference Publication, Vol. 2, pp. 532-536, Aug 2001, Dayton, USA.
  6. Atitallah, A. B. ; Kadionik, P. ; Ghozzi, F. ; Nouel, P. ; Masmoudi, N. ; Marchegay, P. , "Optimization and Implementation on Fpga of the DCT/IDCT Algorithm" IEEE International Conference on Acoustics, Speech and Signal Processing, vol. 3 pp. May 2006. Toulouse, France.
  7. Giovanni Betta, Senior Member, IEEE, Consolatina Liguori, Member, IEEE, and Antonio Pietrosanto, Member, IEEE, "A Multi-Application FFT Analyzer Based on a DSP Architecture", IEEE International Transactions on Instrumentation And Measurement, vol. 50, Issue: 3, pp. 825 - 832, Jun 2001.
  8. S. Akrouf, M. A. Sehili, A. Chakhchoukh, M. Mostefai and C. Youssef, "Face recognition using PCA and DCT," 5th International Conference on MEMS, NANO, and smart systems (ICMENS), , pp. 15-19 , 2009.
  9. Brown, Richard B. ; Lomax, Ronald J. ; Carichner, Gordon A. ; Drake, Alan J. "A microprocessor design project in an introductory VLSI course" IEEE Trans. Educ. , vol. 43, pp. 353 – 361, Aug 2000.
  10. John L. Hennessy, and David A. Patterson, 2006. "Computer Architecture A Quantitative Approach",
  11. Leon W. Couch, 1997. Digital and Analog Communication Systems, Prentice Hall. New Jersey.
  12. Don Anderson, 1997. Universal Serial Bus System Architecture. Addison Wesley. Boston.
Index Terms

Computer Science
Information Sciences

Keywords

Control Unit (CU) General Purpose Register (GPR) Register Set (RS) Multiply and accumulates (MACs) Very Large Instruction Word (VLIW)

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