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Reseach Article

LDPC Architecture for Improved BER in Wireless Networks

by Maria Rubiston. M
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 69 - Number 16
Year of Publication: 2013
Authors: Maria Rubiston. M
10.5120/12046-8101

Maria Rubiston. M . LDPC Architecture for Improved BER in Wireless Networks. International Journal of Computer Applications. 69, 16 ( May 2013), 18-24. DOI=10.5120/12046-8101

@article{ 10.5120/12046-8101,
author = { Maria Rubiston. M },
title = { LDPC Architecture for Improved BER in Wireless Networks },
journal = { International Journal of Computer Applications },
issue_date = { May 2013 },
volume = { 69 },
number = { 16 },
month = { May },
year = { 2013 },
issn = { 0975-8887 },
pages = { 18-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume69/number16/12046-8101/ },
doi = { 10.5120/12046-8101 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:30:26.044782+05:30
%A Maria Rubiston. M
%T LDPC Architecture for Improved BER in Wireless Networks
%J International Journal of Computer Applications
%@ 0975-8887
%V 69
%N 16
%P 18-24
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

To achieve high throughput in wireless networks a partial parallel LDPC decoder is proposed in this paper. For fully-parallel decoders, it suffers from large hardware complexity caused by a large set of processing units and complex interconnections. In wireless networks coding complexity and routing congestion can be reduced by designing the decoder with partially-parallel architecture. The partially-parallel architecture with Split Row algorithm reduces the total global wire length by about 26% without any hardware overhead and increasing the throughput by 60% and 71% in wireless networks.

References
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Index Terms

Computer Science
Information Sciences

Keywords

LDPC-Low Density Parity Check Decoder VN-Variable Node PU-Processing Unit WNs-Wireless Networks CHNU-Check Node Unit CNU-Control Node Unit MU-Memory Unit AGU-Automatic Gain Unit SNR-Signal to Noise Ratio SP-Split Col-Column Mem-Memory BER-Bit Error Rate