We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 December 2024
Reseach Article

LDPC Architecture for Improved BER in Wireless Networks

by Maria Rubiston. M
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 69 - Number 16
Year of Publication: 2013
Authors: Maria Rubiston. M
10.5120/12046-8101

Maria Rubiston. M . LDPC Architecture for Improved BER in Wireless Networks. International Journal of Computer Applications. 69, 16 ( May 2013), 18-24. DOI=10.5120/12046-8101

@article{ 10.5120/12046-8101,
author = { Maria Rubiston. M },
title = { LDPC Architecture for Improved BER in Wireless Networks },
journal = { International Journal of Computer Applications },
issue_date = { May 2013 },
volume = { 69 },
number = { 16 },
month = { May },
year = { 2013 },
issn = { 0975-8887 },
pages = { 18-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume69/number16/12046-8101/ },
doi = { 10.5120/12046-8101 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:30:26.044782+05:30
%A Maria Rubiston. M
%T LDPC Architecture for Improved BER in Wireless Networks
%J International Journal of Computer Applications
%@ 0975-8887
%V 69
%N 16
%P 18-24
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

To achieve high throughput in wireless networks a partial parallel LDPC decoder is proposed in this paper. For fully-parallel decoders, it suffers from large hardware complexity caused by a large set of processing units and complex interconnections. In wireless networks coding complexity and routing congestion can be reduced by designing the decoder with partially-parallel architecture. The partially-parallel architecture with Split Row algorithm reduces the total global wire length by about 26% without any hardware overhead and increasing the throughput by 60% and 71% in wireless networks.

References
  1. M. MariaRubiston, Rajasekar. B, Logashanmugam. E "High Performance LDPC Architecture for Wireless Networks"International conference on Innovations in Intelligent Instrumentation Optimization & Signal Processing, Karunya University,1st & 2nd March 2013, pp. 48-52.
  2. Y. Chen, K. K. Parhi, "Overlapped message passing for quasi-cyclic low-density parity check codes," IEEE Trans. Circuits and Syst. I, vol. 51, pp. 1106-1113, Jun. 2004
  3. Banksby, A. J. , Howland, C. J. A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder. IEEE J. Solid-State Circuits 2002, 37, 404–412.
  4. Quaglio, F. ; Vacca, F. ; Castellano, C. ; Tarable, A. ; Masera, G. Interconnection framework for high-throughput, flexible LDPC decoders. In Proceedings of the Design, Automation and Test in Europe (DATE '06), Munich, Germany, 6–10 March 2006; pp. 1–6.
  5. Moussa, H. ; Baghdadi, A. ; Jezequel, M. Binary de bruijn on-chip network for a flexible multiprocessor LDPC decoder. In Proceedings of the 45th Annual Design Automation Conference, Anaheim, CA, USA, 9–13 June 2008; pp. 429–434.
  6. Shih, X. Y. ; Zhan, C. Z. ; Wu, A. Y. A 7. 39 mm, 2 76 mW (1944, 972) LDPC Decoder Chip for IEEE 802. 11n Applications. In Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC '08), Fukuoka, Japan, 3–5 November 2008; pp. 301–304.
  7. Muller, S. ; Schreger, M. ; Kabutz, M. ; Alles, M. ; Kienle, F. ; Wehn, N. A novel LDPC decoder for DVB-S2 IP. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '09), Nice, France, 20–24 April 2009; pp. 1308–1313.
  8. Xiang, B. ; Bao, D. ; Huang, S. ; Zeng, X. An 847-955Mb/s 342-397mWdual-path fully-overlapped QC-LDPC decoder for WiMAX system in 0. 13 ?m CMOS. IEEE J. Solid-State Circuits 2011, 46, 1416–1432.
  9. Lechner, G. ; Sayir, J. ; Rupp, M. Efficient DSP implementation of an LDPC decoder. In Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP '04), Montreal, QC, Canada, 17–21 May 2004; pp. 665–668.
  10. M. Karkooti, P. Radosavljevic, and J. R. Cavallaro. Con?gurable, high throughput, irregular LDPC decoder architecture: Tradeo? analysis and implementation. In ASAP, pages 360 –367, Sep. 2006.
  11. Zhengya Zhang, V. Anantharam, M. J. Wainwright, and B. Nikolic. An e?cient 10GBASE-T ethernet LDPC decoder design with low error ?oors. Solid-State Circuits, IEEE Journal of, 45(4):843–855, Apr. 2010.
  12. R. Tanner, "A recursive approach to low complexity codes," IEEE Transaction of Information Theory, vol. 27, pp. 533–547, Sept. 1981.
  13. R. El Alami, C. B. Gueye, M. Boussetta, M. Mrabti and M. Zouak, "Reduced complexity of decoding algorithm for Irregular LDPC Codes using Split Row Method" accepted in Proc. Int. Conf. on Multimedia Computing and Systems, Ouarzazate, Morocco, Apr 2010
  14. T. Mohsenin and B. Baas, "Split-row: a reduced complexity, high throughput LDPC decoder architecture," in Proc. ICCD, Oct. 2006.
  15. T. Mohsenin and B. Baas, "High-throughput LDPC decoders using a multiple Split-Row method," in ICASSP, 2007, vol. 2, pp. 13–16.
Index Terms

Computer Science
Information Sciences

Keywords

LDPC-Low Density Parity Check Decoder VN-Variable Node PU-Processing Unit WNs-Wireless Networks CHNU-Check Node Unit CNU-Control Node Unit MU-Memory Unit AGU-Automatic Gain Unit SNR-Signal to Noise Ratio SP-Split Col-Column Mem-Memory BER-Bit Error Rate