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Reseach Article

Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic

by Lakshay Suri, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, Geetanjali Sharma
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 69 - Number 10
Year of Publication: 2013
Authors: Lakshay Suri, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, Geetanjali Sharma
10.5120/11881-7696

Lakshay Suri, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, Geetanjali Sharma . Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic. International Journal of Computer Applications. 69, 10 ( May 2013), 32-35. DOI=10.5120/11881-7696

@article{ 10.5120/11881-7696,
author = { Lakshay Suri, Devesh Lamba, Kunwar Kritarth, Bhavna Ghai, Geetanjali Sharma },
title = { Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic },
journal = { International Journal of Computer Applications },
issue_date = { May 2013 },
volume = { 69 },
number = { 10 },
month = { May },
year = { 2013 },
issn = { 0975-8887 },
pages = { 32-35 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume69/number10/11881-7696/ },
doi = { 10.5120/11881-7696 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:29:55.449649+05:30
%A Lakshay Suri
%A Devesh Lamba
%A Kunwar Kritarth
%A Bhavna Ghai
%A Geetanjali Sharma
%T Design of High Performance and Power Efficient 16-bit Square Root Carry Select Adder using Hybrid PTL/CMOS Logic
%J International Journal of Computer Applications
%@ 0975-8887
%V 69
%N 10
%P 32-35
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In today's techno-savvy world the need of the hour is to develop devices which are power efficient as well as occupy very less area. VLSI circuits have proved to be the vital choice for most of the design engineers in order to reduce power consumption in any device. The most basic operation in any processor circuitry involves addition. Carry Select Adder (CSA) is a high speed adder and its structure reveals that there exists a possibility of reducing area and power dissipation of the circuit. This paper presents power and delay analysis of 16-Bit Square Root CSA implemented through Hybrid PTL/CMOS logic . It examines the performance of the proposed design in terms of area, delay, power in 90nm CMOS process technology. The result shows that proposed Square Root CSA structure is better in terms of area, power and Power Delay Product (PDP) than others.

References
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Index Terms

Computer Science
Information Sciences

Keywords

Power dissipation PDP adders hybrid PTL/CMOS