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Reseach Article

FPGA Implementation of Reed-Solomon Encoder and Decoder for Wireless Network 802.16

by Priyanka Dayal, Rajeev Kumar Patial
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 68 - Number 16
Year of Publication: 2013
Authors: Priyanka Dayal, Rajeev Kumar Patial
10.5120/11667-7263

Priyanka Dayal, Rajeev Kumar Patial . FPGA Implementation of Reed-Solomon Encoder and Decoder for Wireless Network 802.16. International Journal of Computer Applications. 68, 16 ( April 2013), 42-45. DOI=10.5120/11667-7263

@article{ 10.5120/11667-7263,
author = { Priyanka Dayal, Rajeev Kumar Patial },
title = { FPGA Implementation of Reed-Solomon Encoder and Decoder for Wireless Network 802.16 },
journal = { International Journal of Computer Applications },
issue_date = { April 2013 },
volume = { 68 },
number = { 16 },
month = { April },
year = { 2013 },
issn = { 0975-8887 },
pages = { 42-45 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume68/number16/11667-7263/ },
doi = { 10.5120/11667-7263 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:28:04.519411+05:30
%A Priyanka Dayal
%A Rajeev Kumar Patial
%T FPGA Implementation of Reed-Solomon Encoder and Decoder for Wireless Network 802.16
%J International Journal of Computer Applications
%@ 0975-8887
%V 68
%N 16
%P 42-45
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

A new class of cyclic codes that is Reed-Solomon codes are discussed for IEEE 802. 16 wireless networks. Reed-Solomon codes are used for the error detection and correction in communication systems. This is important in information theory and coding to correct burst errors. Here Reed-Solomon code for wireless network 802. 16 is synthesized using VHDL on Xilinx and simulated on ISE simulator. The Reed-Solomon encoder has been checked for different error-correcting capabilities that is 4, 6, 8 etc. Reed-Solomon decoder for IEEE 802. 16 network is synthesized on VHDL for error detection and correction. Here pipelining is introduced in Reed-Solomon decoder to improve the performance. The performance of Reed-Solomon encoder RS (255,239) for IEEE 802. 16 is shown and Reed-Solomon decoder is checked for both RS(255,243) and RS(255,239) and synthesizable on FPGA.

References
  1. National Aeronautics and Space Administration (NASA) technical reports, "Tutorial on Reed-Solomon error correction coding", Lyndon B. Johnson Space Center Houston, 1990.
  2. Reed, I. S. and Solomon, G. , "Polynomial Codes Over Certain Finite Fields," SIAM Journal of Applied Math. , vol. 8, pp. 300-304, 1960.
  3. IEEE draft for "Implementing an IEEE Std. 802. 16- Compliant FEC Decoder", M-WP-IEEE802. 16-1. 0, ver. 1. 0, December 2001.
  4. Sklar, B. , Digital Communications: Fundamentals and Applications, Second Edition (Upper Saddle River, NJ: Prentice-Hall, 2001).
  5. Aqib. Al Azad, Minhazul. Huq, Iqbalur, Rahman Rokon, "Efficient Hardware Implementation of Reed Solomon Encoder and Decoder in FPGA using Verilog", International Conference on Advancements in Electronics and Power Engineering (ICAEPE'2011) Bangkok Dec. , 2011.
  6. Lamia Chaari, Mohamed Fourati, Nouri Masmoudi, Lotfi Kamoun, "A Reconfigurable Fec System Based On Reed-Solomon Codec For Dvb And 802. 16 Network", Issue 8, Volume 8, August 2009.
  7. Joel Sylvester, "Reed Solomon Codes", Elektrobit, January 2001.
  8. Bhawna Tiwari, Rajesh Mehra, "Design and Implementation of Reed Solomon Decoder for 802. 16 Network using FPGA" 978-1-4673-1318, IEEE 2012.
  9. Dilip V. Sarwate, Fellow, IEEE, and Naresh R. Shanbhag, Member, IEEE, "High-Speed Architectures for Reed–Solomon Decoders", IEEE Transactions On Very Large Scale Integration (VLSI) Systems, VOL. 9, NO. 5, OCTOBER 2001.
  10. E. R. Berklamp," Algebric coding theory, McGraw-Hill, New york, 1968: revised edition Aegean Park Press, Laguna Lills, CA, 1984.
  11. Y. Sugiyama, M. Kasahara, S. Hirasawa, and T. Namekawa, "A method for solving key equation for decoding Goppa codes," Information and Control, vol. 27, pp. 87–99, Jan. 1975.
  12. Peter J. Ashenden, "The Designer's Guide to VHDL", Second Edition, Morgan Kaufmann Publishers, 2004.
  13. Donald G. Bailey, "Design for Embedded Image Processing on FPGA'S" 2011.
Index Terms

Computer Science
Information Sciences

Keywords

Generator polynomial Syndrome calculation Berkelamp-massey algorithm Chien search error-correction wireless network 802. 16 Pipelining VHDL FPGA