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Reseach Article

Modified Booth Multiplier using Wallace Structure and Efficient Carry Select Adder

by Neeta Sharma, Ravi Sindal
International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 68 - Number 13
Year of Publication: 2013
Authors: Neeta Sharma, Ravi Sindal
10.5120/11643-7130

Neeta Sharma, Ravi Sindal . Modified Booth Multiplier using Wallace Structure and Efficient Carry Select Adder. International Journal of Computer Applications. 68, 13 ( April 2013), 39-42. DOI=10.5120/11643-7130

@article{ 10.5120/11643-7130,
author = { Neeta Sharma, Ravi Sindal },
title = { Modified Booth Multiplier using Wallace Structure and Efficient Carry Select Adder },
journal = { International Journal of Computer Applications },
issue_date = { April 2013 },
volume = { 68 },
number = { 13 },
month = { April },
year = { 2013 },
issn = { 0975-8887 },
pages = { 39-42 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume68/number13/11643-7130/ },
doi = { 10.5120/11643-7130 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:27:46.928089+05:30
%A Neeta Sharma
%A Ravi Sindal
%T Modified Booth Multiplier using Wallace Structure and Efficient Carry Select Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 68
%N 13
%P 39-42
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The multiplier forms the core of systems such as FIR filters, Digital Signal Processors and Microprocessors etc. This paper presents a model of two different 16X16 bit multipliers. First is Radix-4 Multiplier with SQRT CSLA and Second one is Radix -4 multiplier with Modified SQRT CSLA. Modified Booth Algorithm is used for Partial Products Generation. Wallace Tree Structure is used to accumulate partial Products. SQRT Carry Select Adder is used for addition of last two rows. SQRT Carry Select Adder uses non uniform block size & Modified SQRT Carry Select Adder uses non-uniform block size with Binary to excess one Converter . Both the adders proved to be fast as compared to regular carry select adder. An efficient VHDL code has been written & successfully synthesized & Simulated using Xilinx ISE 12. 1. Simulation results shows that the delay of both the multipliers is reduced & the number of logic levels is also reduced with slight increase in number of slices & LUTS as compared to multiplier that uses regular carry select adder.

References
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Index Terms

Computer Science
Information Sciences

Keywords

VHDL Booth Encoder Carry Save Adder Wallace tree SQRT Carry Select Adder BEC