We apologize for a recent technical issue with our email system, which temporarily affected account activations. Accounts have now been activated. Authors may proceed with paper submissions. PhDFocusTM
CFP last date
20 November 2024
Call for Paper
December Edition
IJCA solicits high quality original research papers for the upcoming December edition of the journal. The last date of research paper submission is 20 November 2024

Submit your paper
Know more
The week's pick
Responsive image
Improved Shuffled Frog Leaping Algorithm with Self-Adaptive Shuffling for Fuzzy Logic PD+G Controller Optimization in Robotic Manipulators

Duc Hoang Nguyen
Random Articles
Reseach Article

FIR Filter Designing using Xilinx System Generator

by Anurag Aggarwal, Astha Satija, Tushar Nagpal
journal cover thumbnail

International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 68 - Number 11
Year of Publication: 2013
Authors: Anurag Aggarwal, Astha Satija, Tushar Nagpal
10.5120/11625-7096

Anurag Aggarwal, Astha Satija, Tushar Nagpal . FIR Filter Designing using Xilinx System Generator. International Journal of Computer Applications. 68, 11 ( April 2013), 37-41. DOI=10.5120/11625-7096

@article{ 10.5120/11625-7096,
author = { Anurag Aggarwal, Astha Satija, Tushar Nagpal },
title = { FIR Filter Designing using Xilinx System Generator },
journal = { International Journal of Computer Applications },
issue_date = { April 2013 },
volume = { 68 },
number = { 11 },
month = { April },
year = { 2013 },
issn = { 0975-8887 },
pages = { 37-41 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume68/number11/11625-7096/ },
doi = { 10.5120/11625-7096 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:27:34.841503+05:30
%A Anurag Aggarwal
%A Astha Satija
%A Tushar Nagpal
%T FIR Filter Designing using Xilinx System Generator
%J International Journal of Computer Applications
%@ 0975-8887
%V 68
%N 11
%P 37-41
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Xilinx System generator is used to design efficient DSP algorithm on FPGA. In this paper Finite Impulse Response (FIR) filter is designed using Simulink in Xilinx System generator. The filters have been designed using Distributed Arithmetic (DA) Algorithm. This design has been further synthesized on Xilinx Virtex-4 FPGA kit. Finally comparison is done between the results obtained from the software simulations and those from FPGA using hardware co-simulation.

References
  1. Jitendra Kumar Das, "Low power digital filter implementation in FPGA for hearing aid application", A thesis submitted to National Institute of Technology Rourkela
  2. Sanjit K. Mitra, " Digital Signal Processing : A Computer based approach" , McGraw Hill, 2006.
  3. A. Oppenheim and R. Schafer, "Digital Signal Processing, "Prentice-Hall, Inc. , 2009.
  4. A. Croisier, D. J. Esteban, M. E. Levilion, and V. Rizo, "Digital Filter for PCM Encoded Signals", U. S. Patent No. 3,777,130, issued April, 1973.
  5. H. Yoo, and D. Anderson, "Hardware-Efficient Distributed Arithmetic Architecture for High-Order Digital Filters", in Proceedings of IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.
  6. Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner, FPGA Implementation of High Speed FIR Filters Using Add and Shift Method, IEEE 2006.
  7. Chi-Jui Chou, Satish Mohanakrishnan, Joseph B. Evans, FPGA implementation of digital filters, Proc. of ICSPAT, 1993.
  8. MathWorks,Simulink, http://www. mathworks. com/products/simulink/
  9. Xilinx system generator, basic tutorial, www. xilinx. com
  10. Harish V. Dixit , Dr. Vikas Gupta, International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622,Vol. 2, Issue 5, September- October 2012, pp. 303-307.
Index Terms

Computer Science
Information Sciences

Keywords

Finite Impulse Response (FIR) Distributed Algorithm (DA) Field Programmable Gate Array (FPGA) Digital Signal Processing (DSP) Analog-to-Digital Converter (ADC)

Powered by PhDFocusTM