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Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder
by
Vishnupriya. A,
Sudarmani. R
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 67 - Number 6 |
| Year of Publication: 2013 |
| Authors: Vishnupriya. A, Sudarmani. R |
10.5120/11401-6717
|
Vishnupriya. A, Sudarmani. R . Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder. International Journal of Computer Applications. 67, 6 ( April 2013), 33-38. DOI=10.5120/11401-6717
@article{
10.5120/11401-6717,
author = {
Vishnupriya. A,
Sudarmani. R
},
title = { Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder },
journal = {
International Journal of Computer Applications
},
issue_date = { April 2013 },
volume = { 67 },
number = { 6 },
month = { April },
year = { 2013 },
issn = { 0975-8887 },
pages = {
33-38
},
numpages = {9},
url = {
https://ijcaonline.org/archives/volume67/number6/11401-6717/
},
doi = { 10.5120/11401-6717 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:23:59.385273+05:30
%A Vishnupriya. A
%A Sudarmani. R
%T Efficient Serial Multiplier Design using Ripple Counters,Kogge-Stone Adder and Full Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 67
%N 6
%P 33-38
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract
High speed and low power multiplier circuits are highly demanded in VLSI design. In this paper, a new approach for high speed and low power multiplier design with less number of gate counts is proposed. In the Ripple Counter–based multiplier design, the number of computational clock cycles is reduced to n for n * n multiplication where n is the word length or the number of bits, which was 2n in the conventional CSAS multiplier. The Ripple Carry Adder (RCA) in the Counter-based design is replaced with Kogge-Stone adder (KSA) for reducing the average connection delay. For reducing the total equivalent gate count and power, the full adder with alternate logic is implemented along with KSA in the multiplier architecture. In our paper, 27. 21% and 31. 53% of the total power has been reduced for unsigned and signed number multiplication respectively.
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Index Terms
Computer Science
Information Sciences
Keywords