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Area Efficient High Speed and Low Power MAC Unit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 67 - Number 23 |
| Year of Publication: 2013 |
| Authors: K. Kalaiselvi, H. Mangalam |
10.5120/11539-7414
|
K. Kalaiselvi, H. Mangalam . Area Efficient High Speed and Low Power MAC Unit. International Journal of Computer Applications. 67, 23 ( April 2013), 40-44. DOI=10.5120/11539-7414
Abstract
With the growing importance of electronic products in day-to-day life, the need for portable electronic products with low power consumption largely increases. In this paper, an area efficient high speed and low power Multiply Accumulator unit (MAC) with carry look-ahead adder (CLA) as final adder is being designed. In the same MAC architecture design in final adder stage of partial product unit the carry save adder(CSA), carry select adder(CSLA) and carry skip adder(CSKPA) are also used instead of CLA to compare the power and performance. These MAC designs were simulated and synthesized using Xilinx 8. 1. The simulation result shows that the MAC design with CLA has area reducing by 16. 7%, speed increase by 1. 95% and the consumed power reducing by 0. 5%.
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