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High-Speed 64-Bit Binary Comparator using Two Stages with Two Different Logic Styles
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 67 - Number 14 |
| Year of Publication: 2013 |
| Authors: Anjuli, Satyajit Anand |
10.5120/11462-7070
|
Anjuli, Satyajit Anand . High-Speed 64-Bit Binary Comparator using Two Stages with Two Different Logic Styles. International Journal of Computer Applications. 67, 14 ( April 2013), 16-21. DOI=10.5120/11462-7070
Abstract
High-speed 64-bit binary comparator using two stages with two different logic styles is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on delay. Means some modifications have been done in existing 64-bit binary comparator design to improve the speed of the circuit. Comparison between modified and existing 64-bit binary comparator designs is calculated by simulation that is performed at 90nm technology in Tanner EDA Tool.
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