Power dissipation in CMOS circuits has put forth many technical challenges for VLSI design engineers. Dynamic power and leakage power have increased with increase in frequency of operation and transistor scaling. Signal and image processing applications require FIR filter as a sub system which has multipliers and adders as sub units. Reducing power dissipation in FIR filter will reduce power dissipation in complex circuits. In this paper, we present design and analysis of FIR filter optimizing area, power and speed performances. The low power techniques and area optimization techniques as recommended by EDA tool vendors are evaluated and optimum constraints are chosen to get the best estimation of power and speed performances. an 8-bit FIR filter is designed using Matlab FDA tool, the HDL model developed I synthesized using ASIC design tools and physical design is carried out. Various optimization techniques at every stage is used to constrain the design for optimum implementation. Choice of multipliers and adders and their impact on power is estimated. The design oriented techniques adopted to achieve power savings up to 36% using the clock gating and using the data path operator isolation here, 7% of the power has been saved. Power targets achieved would be compared to match quantitatively with the power numbers of the same design at gate level netlist after synthesis and gate level netlist after Placement & Routing.

RTL power early estimation Design Oriented Reduction techniques