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Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique

by Anjali Sharma, Rajesh Mehra
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 66 - Number 4
Year of Publication: 2013
Authors: Anjali Sharma, Rajesh Mehra
10.5120/11071-5992

Anjali Sharma, Rajesh Mehra . Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique. International Journal of Computer Applications. 66, 4 ( March 2013), 15-22. DOI=10.5120/11071-5992

@article{ 10.5120/11071-5992,
author = { Anjali Sharma, Rajesh Mehra },
title = { Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique },
journal = { International Journal of Computer Applications },
issue_date = { March 2013 },
volume = { 66 },
number = { 4 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = { 15-22 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume66/number4/11071-5992/ },
doi = { 10.5120/11071-5992 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:21:26.438980+05:30
%A Anjali Sharma
%A Rajesh Mehra
%T Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 66
%N 4
%P 15-22
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper an area and power efficient 9T adder design has been presented by hybridizing PTL and GDI techniques. The proposed adder design consist of 5 NMOS and 4 PMOS. A PTL based 5T XOR-XNOR module has been proposed to improve area at 120 nm and 90nm technology and compared with the previous XOR-XNOR design. The proposed Hybrid full adder design is based on this area efficient 5T XOR-XNOR module design. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the proposed full adder. XOR-XNOR modules outputs act as input to Carry and Sum module which has been implemented by the GDI MUX. The proposed adder has been designed and simulated using DSCH 3. 1 and Microwind 3. 1 on 120nm and 65nm technology. Also the simulation of layout and parametric analysis has been done for the proposed full adder design. Power and current variation with respect to the supply voltage and temperature has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed hybrid adder is 98. 5µm2 on 120nm technology. At 1. 2V input supply voltage the proposed adder has shown an improvement of 76. 9% in power and 74. 82% in current on BSIM-4 120nm technology.

References
  1. N. Weste and K. Eshraghian, (2002) Principles of CMOS VLSI Design: A System Perspective Reading, Pearson Education, Addison–Wesley.
  2. Sung-Mo Kang, Yusuf Leblebici, (2003) CMOS Digital Integrated Circuits: Analysis and Design, TATA Mc GRAW-HILL.
  3. Etienne Sicard, Sonia Delmas Bendhia, Basic of CMOS Cell Design, TATA Mc GRAW-HILL.
  4. Etienne Sicard, Sonia Delmas Bendhia, Advance of CMOS Cell Design, TATA Mc GRAW-HILL.
  5. Chip-Hong Chang, Jiangmin Gu, and Mingyan Zhang "A Review of 0. 18-_m Full Adder Performances for Tree Structured Arithmetic Circuits," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume: 13, no: 6, pp. -686 – 695, 2005.
  6. Sumeer Goel, Ashok Kumar, Magdy A. Bayouni, "Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 14, No. 12, pp. 1309-1321,2006.
  7. Chiou-Kou Tung; Yu-Cherng Hung; Shao-Hui Shieh; Guo-Shing Huang," A Low -Power High-speed Hybrid CMOS Full Adder For Embedded System," IEEE transactions on Design and Diagnostics of Electronic Circuits and Systems ,vol. 13, No. 6, pp. -1 – 4, 2007.
  8. Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwari, "New Design Methodologies for High Speed Mixed Mode Full Adder Circuits," International Journal of VLSI and Communication Systems, Vol. 2, No. 2, pp. - 78-98, 2011.
  9. Subodh Wairya, Rajendra Kumar Nagaria ,Sudarshan Tiwari, "Comparative Performance Analysis of XOR/XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design ", International Journal Of VLSI Design & Communication System, pp. -221-242, 2012.
  10. Aguirre-Hernandez, M. Linares- Aranda, "CMOS Full- Adder For Energy-Efficient Arithmetic Applications," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. -9, No. 4, pp. -718 – 721, 2011.
  11. Mohammad Javad Zavarei, Mohammad Reza Baghbanmanesh, Ehsan Kargaran, Hooman Nabovati, Abbas Golmakani, "Design of New Full Adder Cell Using Hybrid- CMOS Logic Style", IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp. -451-454, Nov 2011.
  12. P. Sreenivasulu, Khasim bee bi, M. V. Narasimha Reddy, "Comparison of Transistor count Optimized Full adders with modified CMOS Full adders," International Journal of Emerging Technology and Advanced Engineering, Vol. 2, No. 7, pp. -300-303, July 2012.
  13. R. UMA,Vidya Vijayan, M. Mohanapriya, Sharon Paul, "Area, Delay and Power Comparison of Adder Topologies," International Journal of VLSI design & Communication Systems (VLSICS), Vol. 3, No. 1, pp. -153-168, February 2012.
  14. Jian-Fei Jiang, Zhi-Gang Mao,Wei-Feng He, Qin Wang, "A New Full Adder Design For Tree Structured Arithmetic Circuits," International conference on computer engineering and technology, pp. -246-249, 2010.
  15. Manoj Kumar R and Krishna Murthy M, "A Low Power Area Efficient Design for 1-bit Full Adder Cell," International Journal of Computer Science and Information Technologies, Vol. 3, no. 3, pp. -,4139-4142, 2012.
  16. Subodh Wairya , Garima Singh, Vishant, R. K. Nagaria and S. Tiwari, "Design Analysis of XOR (4T) based Low Voltage CMOS Full Adder Cell," In Proceeding of IEEE International Conference on Current Trends In Technology (NUiCONE), pp. 1-7, 2011.
  17. Fartash Vasefi ,Z. Abid, "Low Power N-Bit Adders And Multiplier Using Lowest-Number-Of-Transistor 1-Bit Adders," IEEE Conference on Electrical and Computer Engineering, ,pp. -1731-1734, 2005.
  18. Jin-Fa Lin Yin-Tsung Hwang, Ming-Hwa Sheu and Cheng-Che Ho, "A High Speed and Energy Efficient Full Adder Design Using Complementary & Level Restoring Carry Logic," IEEE International Symposium on Circuits and Systems, pp. -2705-2708, 2006.
  19. Jin-Fa-Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, and Cheng-Che Ho, "A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design," IEEE Transaction on Circuits and Systems I, Vol. 54, No. 5, pp. 1050-1059, 2007.
  20. Shamima Khatoon, "A Novel Design for Highly Compact Low Power Area Efficient 1-Bit Full Adders," International Journal of Advances in Engineering & Technology, Vol. -4, No. 2, pp-464-473, Sept 2012.
  21. G. Ramana Murthy, C. Senthilpari , P. Velrajkumar, Lim Tien Sze, "Interconnect Analysis of a Novel Multiplexer Based Full-Adder Cell for Power and Propagation Delay Optimizations," International Journal of Electronics and Electrical Engineering, Vol. 3, No. 5, pp. - 288-292, 2012.
  22. Manoj Kumar, Sandeep K. Arya and Sujata Pandey, "Single bit full adder design using 8 transistors with novel 3 transistors XNOR gate," International Journal of VLSI design & Communication Systems (VLSICS), Vol. 2, No. 4, pp. -47-59, December 2011.
  23. Shiv Shankar Mishra, Adarsh Kumar Agrawal and R. K. Nagaria, "A comparative performance analysis of various CMOS design techniques for XOR and XNOR circuits," International Journal on Emerging Technologies, Vol. 2, No. 4, pp. 1-10,2010
  24. Agrawal, A. K. ; Mishra, S. ; Nagaria, R. K. , "Proposing a novel low-power high-speed mixed GDI Full Adder topology,"International Conference on Power, Control and Embedded Systems, pp. 1 – 6,2010
  25. MA Elgamel, S. Goel, MA Bayoumi, Noise tolerant low voltage XOR-XNOR for fast arithmetic, in Proc. Great Lake Symp . VLSI, Washington DC, Apr. , 28-29, pp. 285-288(2003).
  26. S. Goel, S. Gollamudi, A. Kumar, and M. Bayoumi, On the design of low-energy hybrid CMOS 1-bit full-adder cells, in Proc. Midwest Symp. Circuits Syst. , pp. II-209-212(2004).
  27. Morgenshtein, A. ; Fish, A. ; Wagner, I. A. , "Gate-diffusion input (GDI): A Power Efficient Method for Digital Combinational circuits," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, Vol. 10 , No. 5 ,pp. 566 - 581 , 2002.
  28. Morgenshtein, A. ; Fish, A. ; Wagner, A. , "Gate-diffusion input (GDI)-A novel power efficient method for digital circuits: A Design Methodology," IEEE International Conference, pp. 39 – 43,2001
  29. Microwind and DSCH version 3. 1, User's Manual, Copyright 1997-2007, Microwind INSA France
  30. Po-Ming Lee; Chia-Hao Hsu; Yun-Hsiun Hung, " Novel 10-T full adders realized by GDI structure" Components, Circuits, Devices &Systems ,Engineered Materials, Dielectrics & Plasmas ,pp. 115 - 118 , 2007.
  31. Shahid Jaman, Nahian Chawdhury, Aasim Ullah, Muhammad Foyazur Raham, " A New High Speed-Low Power 12 Transistor Full Adder Design With GDI Technique," international Journal of Science & Engineering Research," Vol. 3,No. 7,2012.
  32. Pakkiraiah Chakali, K Sreeknath Yadav, Dilli Babu S, " A Noval Low Power Binary to Gray Code Converter Using Gate Diffusion Input (GDI), IOSR journal of engineering ,vol. 2, No. 8, pp. 107-111,2012
Index Terms

Computer Science
Information Sciences

Keywords

BSIM CMOS Gate Diffusion Input Pass transistor logic VLSI

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