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Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique

by Anjali Sharma, Rajesh Mehra
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 66 - Number 4
Year of Publication: 2013
Authors: Anjali Sharma, Rajesh Mehra
10.5120/11071-5992

Anjali Sharma, Rajesh Mehra . Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique. International Journal of Computer Applications. 66, 4 ( March 2013), 15-22. DOI=10.5120/11071-5992

@article{ 10.5120/11071-5992,
author = { Anjali Sharma, Rajesh Mehra },
title = { Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique },
journal = { International Journal of Computer Applications },
issue_date = { March 2013 },
volume = { 66 },
number = { 4 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = { 15-22 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume66/number4/11071-5992/ },
doi = { 10.5120/11071-5992 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:21:26.438980+05:30
%A Anjali Sharma
%A Rajesh Mehra
%T Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique
%J International Journal of Computer Applications
%@ 0975-8887
%V 66
%N 4
%P 15-22
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

In this paper an area and power efficient 9T adder design has been presented by hybridizing PTL and GDI techniques. The proposed adder design consist of 5 NMOS and 4 PMOS. A PTL based 5T XOR-XNOR module has been proposed to improve area at 120 nm and 90nm technology and compared with the previous XOR-XNOR design. The proposed Hybrid full adder design is based on this area efficient 5T XOR-XNOR module design. To improve area and power efficiency a cascade implementation of XOR module has been avoided in the proposed full adder. XOR-XNOR modules outputs act as input to Carry and Sum module which has been implemented by the GDI MUX. The proposed adder has been designed and simulated using DSCH 3. 1 and Microwind 3. 1 on 120nm and 65nm technology. Also the simulation of layout and parametric analysis has been done for the proposed full adder design. Power and current variation with respect to the supply voltage and temperature has been performed on BSIM-4 and LEVEL-3 on 120nm. Results show that area consumed by the proposed hybrid adder is 98. 5µm2 on 120nm technology. At 1. 2V input supply voltage the proposed adder has shown an improvement of 76. 9% in power and 74. 82% in current on BSIM-4 120nm technology.

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Index Terms

Computer Science
Information Sciences

Keywords

BSIM CMOS Gate Diffusion Input Pass transistor logic VLSI

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