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Design of a Simple General Purpose Microprocessor with Self-Sleep Buffer
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 66 - Number 20 |
| Year of Publication: 2013 |
| Authors: Esther Rani. T, Rameshwar Rao |
10.5120/11204-6490
|
Esther Rani. T, Rameshwar Rao . Design of a Simple General Purpose Microprocessor with Self-Sleep Buffer. International Journal of Computer Applications. 66, 20 ( March 2013), 41-47. DOI=10.5120/11204-6490
Abstract
In this paper, a general purpose microprocessor is implemented and a self sleep circuit is used to reduce the power. MTCMOS is proven to be the best technique to reduce leakage power in deep submicron regime. Placing sleep transistor in fine grain has its own advantages and disadvantages and global sleep transistor is not practical. So, distributed MTCMOS is considered as better alternative for placing sleep device in the design at block level. As the routing resources are involved even in the distributed, self-sleep is suggested to reduce number of nets and transistors. This is verified in a simple microprocessor that executes eight number of instructions using 90nm technology savings in power and area observed.
References
- S. Mutoh et al. , "1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS," Jour. Solid- State Circuits, vol. 30, pp. 847-854, Aug. 1995.
- J. Kao, A. Chandrakasan, D. Antoniadis, "Transistor sizing issues and tool for multi-threshold CMOS technology," in Proc. IEEE/ACM Design Automation Conf. , pp. 409-414, June 1997.
- J. Kao, S. Narendra, A. Chandrakasan, "MTCMOS hierarchical sizing based on mutual exclusive discharge pattern," in Proc. IEEE/ACM Design Automation Conf. , pp. 495-500, June 1998.
- S. Kim, S. V. Kosonocky, D. R. Knebel, and S. Stawiasz, "Experimental measurement of a novel power gating structure with intermediate power saving mode," in Proc. IEEE Int. Symp. On Low Power Elec. Design, pp. 20-25, August 2004.
- S. Kim, S. V. Kosonocky, D. R. Knebel, "Understanding and minimizing ground bounce during mode transition of power gating structures," in Proc. IEEE Int. Symp. On Low Power Elec. Design, pp. 22-25, August 2003.
- A. Ramalingam, A. Devgan, and D. Z. Pan, "Wakeup scheduling in MTCMOS circuits using successive relaxation to minimize ground bounce," Jour. Of Low Power Electronics, vol. 3, no. 1, 2007.
- Charbel J. Akl and Magdy A. Bayoumi "Sleep buffer for distributed MTCMOS design" in Proc. IEEE/ACM Int. Conference on VLSI design, pp. 673-678, 2008
- C. Long, and L. He, "Distributed sleep transistor network for power reduction," IEEE Trans. VLSI Syst. , vol. 12, no. 9, Sep. 2004.
- Shi, D. Howard, "Sleep transistor design and implementation – simple concepts yet challenges to be optimum," in Proc. Int. Symp. VLSI Design, Automation and Test, pp. 1-4, April 2006.
- V. Khandelwal and A. Srivastava, "Leakage control through fine-grain placement and sizing of sleep transistors," in Proc. IEEE/ACM Int. Conference on CAD, pp. 533-536, 2004.
- Mohab Anis,Shawki Areibi and Mohamed Elmasry, "Design and Optimization of Multithreshold CMOS(MTCMOS) Circuits", IEEE Trans on CAD of ICs and systems, pp. 1324-1342, 2003.
- Enoch O. Hwang, 2006 "Digital Logic and microprocessor design with VHDL", Thomson publishers.
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