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Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates

by Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A Kulkarni, H R Bhagyalakshmi, M K Venkatesha
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 66 - Number 19
Year of Publication: 2013
Authors: Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A Kulkarni, H R Bhagyalakshmi, M K Venkatesha
10.5120/11193-6325

Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A Kulkarni, H R Bhagyalakshmi, M K Venkatesha . Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates. International Journal of Computer Applications. 66, 19 ( March 2013), 20-24. DOI=10.5120/11193-6325

@article{ 10.5120/11193-6325,
author = { Rakshith Saligram, Shrihari Shridhar Hegde, Shashidhar A Kulkarni, H R Bhagyalakshmi, M K Venkatesha },
title = { Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates },
journal = { International Journal of Computer Applications },
issue_date = { March 2013 },
volume = { 66 },
number = { 19 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = { 20-24 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume66/number19/11193-6325/ },
doi = { 10.5120/11193-6325 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:22:52.889907+05:30
%A Rakshith Saligram
%A Shrihari Shridhar Hegde
%A Shashidhar A Kulkarni
%A H R Bhagyalakshmi
%A M K Venkatesha
%T Design of Fault Tolerant Reversible Multiplexer based Multi-Boolean Function Generator using Parity Preserving Gates
%J International Journal of Computer Applications
%@ 0975-8887
%V 66
%N 19
%P 20-24
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Reversible logic is one of the emerging fields of research in the areas of low power computation, Optical information processing, Fault tolerant system, bio information, quantum computation and nanotechnology. ALU is the most vital component of any processing system and need to consume as much less energy as possible in the mean while must be resistant to faults. In this paper the design of a fault tolerant function generator is brought out that can generate up to 16 different Boolean Functions. This unit is the logical unit of an ALU.

References
  1. R. Landauer,"Irreversibility and Heat Generation in the Computational Process", IBM Journal of Research and Development, 5, pp. 183-191, 1961.
  2. C. H. Bennett, "Logical reversibility of Computation", IBM J. Research and Development, pp. 525-532, November 1973.
  3. R. Feynman, "Quantum Mechanical Computers," Optics News, Vol. 11, pp. 11–20, 1985.
  4. A. Peres, Reversible logic and quantum computers, Phys. Rev. A 32 (1985) 3266–3276.
  5. E. Fredkin and T. Toffoli,"Conservative Logic", Int'l J. Theoretical Physics Vol 21, pp. 219-253, 1982.
  6. H. R. Bhagyalakshmi, M. K. Venkatesha, "An Improved Design of a Multiplier Using Reversible Logic Gates", International Journal of Engineering Science and Technology Vol. 2(8), 2010, 3838-3845.
  7. H. R. Bhagyalakshmi, M. K. Venkatesha," Optimized Reversible BCD adder using new Reversible Logic Gates", Journal of Computing, Vol 2, Issue 2, February 2010
  8. H. R. Bhagyalakshmi, M. K. Venkatesha, "Design of Multifunctional BVMF Reversible logic gate and its applications" Intl. Journal of Computer Applications, Vol 32, No. 3 Oct-2011.
  9. Md. Saiful Islam et. al" Synthesis of fault tolerant Reversible logic" IEEE 2009.
  10. Rakshith Saligram and Rakshith T R "Novel Code Converter employing Reversible Logic" Intl. Journal of Computer Applications, Vol 52, No. 18, Aug 2012.
  11. B. Parhami, "Fault tolerant reversible circuits", Asimolar Conf. Signal systems and computers", October 2006
  12. Krishna Murthy, Gayatri G, Manoj Kumar "Design of Efficient Adder Circuits Using Proposed Parity Preserving Gate (PPPG)" International Journal of VLSI design & Communication Systems (VLSICS) Vol. 3, No. 3, June 2012.
  13. Xuemei Qi and Et. Al, Design of fast fault tolerant reversible signed multiplier, International Journal of the Physical Sciences Vol. 7(17), pp. 2506 - 2514, 23 April, 2012.
Index Terms

Computer Science
Information Sciences

Keywords

Reversible Logic Parity Preserving Gates Multi-Boolean Function Generator Logic Unit Nanotechnology

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