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An Efficient Synchronous Static Memory design for Embedded System

by Ravi Khatwal, Manoj Kumar Jain
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 66 - Number 18
Year of Publication: 2013
Authors: Ravi Khatwal, Manoj Kumar Jain
10.5120/11187-6411

Ravi Khatwal, Manoj Kumar Jain . An Efficient Synchronous Static Memory design for Embedded System. International Journal of Computer Applications. 66, 18 ( March 2013), 39-45. DOI=10.5120/11187-6411

@article{ 10.5120/11187-6411,
author = { Ravi Khatwal, Manoj Kumar Jain },
title = { An Efficient Synchronous Static Memory design for Embedded System },
journal = { International Journal of Computer Applications },
issue_date = { March 2013 },
volume = { 66 },
number = { 18 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = { 39-45 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume66/number18/11187-6411/ },
doi = { 10.5120/11187-6411 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:22:48.587620+05:30
%A Ravi Khatwal
%A Manoj Kumar Jain
%T An Efficient Synchronous Static Memory design for Embedded System
%J International Journal of Computer Applications
%@ 0975-8887
%V 66
%N 18
%P 39-45
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

Custom memory organization are challenging task in the area of VLSI design. This study aims to design high speed and low power consumption memory for embedded system. Synchronous SRAM has been proposed and analyzed using various simulators. Xilinx simulator simulates the Synchronous SRAM memories which can perform efficient read/write capability for embedded systems. Xinix tool also provide the access time that required selecting a word and reading it. Synchronous Static RAM which has easily read /writes capability and performs scheduled read /writes operation in efficient manner.

References
  1. Jain, M. K. , Balakrishnan M. and Kumar, A. , 2005, Integrated on-chip storage evaluation in ASIP synthesis, VLSI Design, 2005, 18th International Conference. pp. 274 – 279.
  2. Panda, P. R. , Dutt, N. D. and Nicoulau, A. , "Data Memory Organization and Optimization In Application Specific Systems",IEEE design & Tests of Computers, May-June 2001, pp. 56-68.
  3. Corre, G. , Senn E. , Iulin, N. and Martin, E. , 2004, Memory aware high-level synthesis for embedded systems, IADIS conference on Applied Computing, Portugal (2004), pp. 499-506.
  4. J. D. Hiser, J. W. Davidson and D. B. Whalley Fast, "Accurate Design Space Exploration of Embedded Systems Memory Configurations", (2007).
  5. Lio, Y. L. , Chen, L. C. , Li, M. L. and Tsay, R. S. , "A Cycle Count Accurate Timing Model for Fast Memory Simulation" 21th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, August 2010.
  6. Yang, S. , Verbauwhede, I. M. "Methodology for Memory Analysis and Optimization in Embedded Systems", (2001).
  7. Xilinx tool Homepage: www. xilinx. com/homepage/.
Index Terms

Computer Science
Information Sciences

Keywords

Embedded System Memory design Memory simulation Xilinx

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