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A New Design of Full Adder based on XNOR-XOR Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 66 - Number 13 |
| Year of Publication: 2013 |
| Authors: Riya Garg, Suman Nehra, B. P. Singh |
10.5120/11142-6224
|
Riya Garg, Suman Nehra, B. P. Singh . A New Design of Full Adder based on XNOR-XOR Circuit. International Journal of Computer Applications. 66, 13 ( March 2013), 7-10. DOI=10.5120/11142-6224
Abstract
This paper presents pre-layout simulations of a proposed 8T full adder design using a proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption hence power-delay product (PDP) over various input voltages and frequencies. It also improves temperature sustainability as compared to the existing 8T full adder. This proves to be a viable option for low power and energy efficient applications. It also shows nearly 82% improvement in threshold loss as compared to the existing 8T full adder. All simulations have been performed on 45nm standard model on Tanner EDA tool version 12. 6.
References
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