The week's pick
Reseach Article
High Throughput LFSR Design for BCH Encoder using Sample Period Reduction Technique for MLC NAND based Flash Memories
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 66 - Number 10 |
| Year of Publication: 2013 |
| Authors: Manikandan. S. K, Sharmitha. E. K, Nisha Angeline. M, Palanisamy. C |
10.5120/11123-6085
|
Manikandan. S. K, Sharmitha. E. K, Nisha Angeline. M, Palanisamy. C . High Throughput LFSR Design for BCH Encoder using Sample Period Reduction Technique for MLC NAND based Flash Memories. International Journal of Computer Applications. 66, 10 ( March 2013), 33-39. DOI=10.5120/11123-6085
Abstract
Error correction is one of the important technique for detecting and correcting errors in communication channels, memories etc. , Errors are associated with all types of memories. But the NAND FLASH memories are competing in the market due to its low power, high density, cost effectiveness and design scalability. As far as the memory is concerned the testing should not consume more time. So, some DSP algorithms are used to overcome the delays by increasing the sampling rate. BCH codes are widely been used for error detection and correction. The generated check bits of the BCH encoder are appended with the message bits to form a codeword. This codeword is sent to the receiver to detect any error during the transmission. One of the main components of BCH encoder is LFSR (Linear Feedback Shift Register). LFSR find its wider application in Built-in-Self-Test, signature analyzer etc. , whereas here it is used to form parity bits to concatenate with message bits for the formation of a codeword. The main advantage of LFSR is that it is simple to construct and it operates at very high clock speed, but its main drawback is that the inputs are given in bit serial. To overcome these drawbacks, DSP algorithms such as unfolding and parallel processing are used by selecting the unfolding factor based on some design criteria. Selecting a better unfolding value reduces the sample period, decreases the clock cycle, and increases the speed, power and the throughput.
References
- R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, "Introduction to flash memory," Proc. IEEE, vol. 91, no. 4, pp. 489–502, Apr. 2003.
- J. Cooke, "The inconvenient truths about NAND flash memory," presented at the Micron MEMCON Presentation, Santa Clara, CA, 2007.
- William Stallings, "Cryptography and Network Security-Principles and Practices, Introduction to Finite Fields", 3rd edition, 2004.
- Ranjan Bose, "Information Theory, Coding and Cryptography".
- K. K. Parhi "VLSI Digital Signal Processing Systems-Design And Implementation".
- Wei Liu, Junrye Rho, and Wongong Sung, "Low- Power High throughput BCH error correction VLSI Design for Multi-Level cell NAND Flash Memories".
- Keshab K. Parhi, "Eliminating the Fan out Bottleneck in Parallel Long Bch Encoders" in proc IEEE, vol. 51. No. 3, march 2004.
- Chao Cheng and Keshab Parhi, "High-Speed Parallel CRC Implementation Based on Unfolding, Pipelining And Retiming", in proc, IEEE, vol. 53, No. 10, October 2006.
- Naresh Reddy, B. Kiran Kumar and K. monisha Sirisha," On the Design of High Speed Parallel CRC Circuits Using DSP Algorithms" in IJCSIT, vol. 3 (5), 2012.
- John G. Proakis Masoud Salehi,"Digital-Communications-Linear block codes, cyclic codes, BCH codes, Reed-Solomon codes," 5th Edition, 2008.
Index Terms
Keywords