The week's pick
Reseach Article
Adiabatic Split Level Charge Recovery Logic Circuit
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 65 - Number 25 |
| Year of Publication: 2013 |
| Authors: Aruna Rani, Poonam Kadam |
10.5120/11272-6487
|
Aruna Rani, Poonam Kadam . Adiabatic Split Level Charge Recovery Logic Circuit. International Journal of Computer Applications. 65, 25 ( March 2013), 18-22. DOI=10.5120/11272-6487
Abstract
This paper describes the design and circuit simulation of split level charge recovery logic (SCRL). In conventional circuits the bits are thrown away for every transformation in the output level, And their associated energy becomes heat, which directly affects the cost of computation by increasing the system overhead required to get rid of the heat causing inconvenience of weight, short battery life etc. SCRL adiabatic logic promises to be an efficient technique to design low power digital VLSI circuit. The power efficiency of SCRL circuit is observed by comparing its performance with static CMOS inverter. A power efficient SCRL CLA is also designed and verified in this paper. Computer simulation using LTSPICE4 is carried out on SCRL circuit's implemented using CMOS technology.
References
- A. G. Dickinson and J. S. Denker,"Adiabatic Dynamic Logic," IEEE J. Solid-state Circuits,vol. 30, pp. 311-315,Mar,1995.
- Yong Moon, Deog-Kyoon Jeong," An Efficient Charge Recovery Logic Circuit ," IEEE J. Solid-State Circuits,vol,31. No 4, April, 1996.
- S. Younis and T. K. Knight, "Asymptotically Zero Energy Split- Level Charge Recovery Logic". Proc. Workshop on low Power Design, pp. 177-182, 1994.
- S. Kim and M. C. Papaefthymiou, "Single-phase source coupled adiabatic logic," Proc. Int. Symp. Low-Power Electronics and Design, pp. 97-99, Aug. 1999
- W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzains, and E. YC. Chou, Low-power digital systems based on adiabatic-switching principles,. IEEE Trans. Very Large Scale Intgr. (VLSI) Syst. , vol. 2, no. 4, pp. 398. 407, April 1994.
- J. S. Denker. A review of adiabatic computing. In Proceedings of the 1994 Symposium on Low Power Electronics/Digest of Technical Papers, pages 94–97, October 1994.
- J. S. Denker, S. C. Avery, A. G. Dickinson, A. Kramer, and T. R. Wik, Adiabatic computing with 2N-2N2D logic family,. in Proc. Int. Workshop Low Power Design, pp. 183. 187, April 1994.
- K. T. Lau and F. Liu, . Improved adiabatic pseudo-domino logic,. Electron. Lett. , vol. 33, no. 25, pp. 2113. 2114, Dec. 1997.
- Y. Ye and K. Roy, . QSERL: Quasi-static energy recovery logic,. IEEE J. Solid-States Circuits, vol. 36, no. 2, pp. 239. 248, Feb. 2001.
- K. Takahashi and M. Mizunuma, . Adiabatic dynamic CMOS logic circuit,. IEICE Trans. Electron. (Japanese Edition), vol. J81-CII, no. 10, pp. 810. 817, Oct. 1998 (Electronics and Communications in Japan Part II (English Translation), vol. 83, no. 5 , pp. 50. 58, April 2000).
- T. Gabara,"Pulsed Power Supply CMOS," Technical Digest IEEE Symposium Low Power Electronics, San Diego, pp. 98- 99, October 1994.
- K. Kaishita, M. Hashizume, H. Yotsuyanagi, and T. Tamesada, . Low power dynamic CMOS logic circuits,. in Shikoku-Section Joint Convention Record of the Institute of Electrical and Related Engineers(Japanese Edition), p. 138, Oct. 2003. ,
- Joonho Lim, Dong-Gyu Kim, and Soo-Ik Chae "A 16-bit Carry-Lookahead Adder Using Reversible Energy Recovery Logic for Ultra-Low-Energy Systems," IEEE J Solid state circuits,vol. 34, no. 6, june. 1999
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