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Area and Timing Analysis of Different PSU’s in P-Match Algorithm for Data Compression in Cache Memories
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 65 - Number 22 |
| Year of Publication: 2013 |
| Authors: Nisha Angeline. M, Shree Subhatra. K, Manikandan. S. K, S. Valarmathy |
10.5120/11214-6251
|
Nisha Angeline. M, Shree Subhatra. K, Manikandan. S. K, S. Valarmathy . Area and Timing Analysis of Different PSU’s in P-Match Algorithm for Data Compression in Cache Memories. International Journal of Computer Applications. 65, 22 ( March 2013), 5-11. DOI=10.5120/11214-6251
Abstract
Microprocessors speeds have been increasing faster than the speed of off-chip memory. In a multi-processor system, if the processor number is increased, then the access time of the memory is also high. Thus a 'wall' is raised between processor number and memory access time. When compared with on chip cache, to access the data, off-chip cache takes one order of magnitude more time. Off chip cache also takes two orders of magnitude more time for executing an instruction, than on chip cache. Care should be taken in cache compression, to increase the processor speed but it should not contradict with the increase in the total chip's power consumption. The compression is based on pattern coding and dictionary based matching and if the pattern matches, the code is chosen. Otherwise the dictionary matching is done. The compressor is composed of Pattern matching and Priority Unit. In this paper three different architectures for the priority selection unit is proposed and their area and timing analysis is done.
References
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