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Hardware Description of Digital Adaptive IIR Filters for Implementing on FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 65 - Number 18 |
| Year of Publication: 2013 |
| Authors: Sahar Moradi, Yousef S. Kavian |
10.5120/11026-5773
|
Sahar Moradi, Yousef S. Kavian . Hardware Description of Digital Adaptive IIR Filters for Implementing on FPGA. International Journal of Computer Applications. 65, 18 ( March 2013), 33-39. DOI=10.5120/11026-5773
Abstract
The hardware description and implementation of adaptive infinite-impulse-response (IIR) filters for real-time applications is an important and challenging designing issue. The aim of this paper is hardware description of digital adaptive IIR filters for implementing on field programmable gate array (FPGA) chips. The direct architecture is considered for IIR filter designing and Equation-Error (EE) Least Mean Square (LMS) adaptive algorithm is employed for updating filter coefficients. Adaptive IIR filter is employed in interference cancellation and inverse system identification applications and the results are compared with finite-impulse-response (FIR) filter in terms of convergence speed, maximum operating frequency, chip area and power dissipation criteria. The VHDL hardware description language is used for providing hardware models and descriptions of algorithms and applications. The results achieved from QUARTUS II synthesize tool on a single STRATIXII chip, EP2S15F484C3, from ALTERA Inc. demonstrate that the adaptive IIR architecture has better performance than adaptive FIR architecture for inverse system identification application while for interference cancellation application adaptive FIR filter works better than adaptive IIR filter.
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