The week's pick
Reseach Article
Hardware Description of Digital Adaptive IIR Filters for Implementing on FPGA
| International Journal of Computer Applications |
| Foundation of Computer Science (FCS), NY, USA |
| Volume 65 - Number 18 |
| Year of Publication: 2013 |
| Authors: Sahar Moradi, Yousef S. Kavian |
10.5120/11026-5773
|
Sahar Moradi, Yousef S. Kavian . Hardware Description of Digital Adaptive IIR Filters for Implementing on FPGA. International Journal of Computer Applications. 65, 18 ( March 2013), 33-39. DOI=10.5120/11026-5773
Abstract
The hardware description and implementation of adaptive infinite-impulse-response (IIR) filters for real-time applications is an important and challenging designing issue. The aim of this paper is hardware description of digital adaptive IIR filters for implementing on field programmable gate array (FPGA) chips. The direct architecture is considered for IIR filter designing and Equation-Error (EE) Least Mean Square (LMS) adaptive algorithm is employed for updating filter coefficients. Adaptive IIR filter is employed in interference cancellation and inverse system identification applications and the results are compared with finite-impulse-response (FIR) filter in terms of convergence speed, maximum operating frequency, chip area and power dissipation criteria. The VHDL hardware description language is used for providing hardware models and descriptions of algorithms and applications. The results achieved from QUARTUS II synthesize tool on a single STRATIXII chip, EP2S15F484C3, from ALTERA Inc. demonstrate that the adaptive IIR architecture has better performance than adaptive FIR architecture for inverse system identification application while for interference cancellation application adaptive FIR filter works better than adaptive IIR filter.
References
- Haykin, S. 2002. Adaptive Filter Theory.
- Bellanger, M. 2001. Adaptive Digital Filters.
- Zhou, J. , Gang, L. , Sun, M. 2006. A Structural View of Stability in Adaptive IIR Filters, IEEE Transactions on Signal Processing, 2006.
- Pan, S. -T. 2011. Evolutionary Computation on Programmable Robust IIR Filter Pole-Placement Design. IEEE Transactions on Instrumentation and Measurement, 2011.
- Zhang, X. , Wang, W. , Yoshikawa, T. , Takei, Y. 2006. Design of IIR orthogonal wavelet filter banks using lifting scheme, IEEE Transactions on Signal Processing, 2006.
- Wolf, W. 2004. FPGA-Based System Design.
- Baese, U. M. 2007. Digital Signal Processing With Field Programmable Gate Arrays.
- Rosado-Muñoz, A. , Bataller-Mompeán, M. , Soria-Olivas, E. , Scarante, C. , Guerrero-Martínez, J. F. 2011. FPGA implementation of an adaptive filter robust to impulsive noise: two approaches, IEEE Transactions on Industrial Electronics, 2011.
- Meher, P. K. , Chandrasekaran, S. , Amira, A. . 2008. FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic, IEEE Transactions on Signal Processing, 2008.
- Nekoei, F. , Kavian, Y. S. , Strobel, O. 2010. Some Schemes of Realization Digital FIR Filters on FPGA for Communication Applications. In Proceeding of the IEEE CriMico conference.
- Ariyadoost, H. , Kavian, Y. S. , Ansari-Asl, K. 2012. Two dimensional systolic adaptive DLMS FIR filters for image processing on FPGA. In Proceeding of 20th IEEE Iranian Conference on Electrical Engineering.
- Rosado-Muñoz, A. , Bataller-Mompea?n, M. , Soria-Olivas, E. , Scarante, C. , Guerrero-Marti?nez, J. 2011. FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches, IEEE Transactions on Industrial Electronics, 2011.
- Benkrid, Abd. S. , Benkrid, K. 2009. Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2009.
- Karabchevsky, S. , Kahana, D. , Ben-Harush, O. , Guterman, H. 2011. FPGA-Based Adaptive Speckle Suppression Filter for Underwater Imaging Sonar, IEEE Journal of Oceanic Engineering, 2011.
- Nekoei, F. , Zargar Talebi, N. , Kavian, Y. S. 2012. FPGA implementation of LMS self correcting adaptive filter (SCAF) and hardware analysis. In Proceeding of the 9th IEEE, IET International Symposium on Communication Systems, Networks and Digital Signal Processing.
- Zhang, Y. , Zheng, D. , Xing, W. , Fan. , S. 2012. Design of IIR filter in capacitive rotary position sensor based on FPGA. In Proceeding of the 8th IEEE International Symposium on Instrumentation and Control Technology.
- Joshi, R. M. , Madanayake, A. , Adikari, J. ,Bruton, L. T. 2012. Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012.
- Arjuna Madanayake, H. L. P. , Bruton, L. T. 2008. A Systolic-Array Architecture for First-Order 3-D IIR Frequency-Planar Filters, IEEE Transactions on Circuits and Systems I, 2008.
- Arjuna Madanayake, H. L. P. , Bruton, L. T. 2007. Low-complexity distributed parallel processor for 2D IIR broadband beam plane-wave filters, Canadian Journal of Electrical and Computer Engineering, 2007.
- Perry, D. L. 2004. VHDL.
- Altera Inc. Power Play Power Analysis. 26 pages. [Online] Cited 2012-08-02. Available at: http://www. altera. com/literature/hb/qts/qts_qii53013. pdf
- Altera Inc. Area and Timing Optimization. 26 pages. [Online] Cited 2012-07-4. Available at:http://www. altera. com/literature/hb/qts/qts_qii2005. pdf.
Index Terms
Keywords