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Logical Effort to Study the Performance of 32-bit Heterogeneous Adder

by Neha Agarwal, Satyajit Anand
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International Journal of Computer Applications
Foundation of Computer Science (FCS), NY, USA
Volume 65 - Number 16
Year of Publication: 2013
Authors: Neha Agarwal, Satyajit Anand
10.5120/11010-6344

Neha Agarwal, Satyajit Anand . Logical Effort to Study the Performance of 32-bit Heterogeneous Adder. International Journal of Computer Applications. 65, 16 ( March 2013), 36-38. DOI=10.5120/11010-6344

@article{ 10.5120/11010-6344,
author = { Neha Agarwal, Satyajit Anand },
title = { Logical Effort to Study the Performance of 32-bit Heterogeneous Adder },
journal = { International Journal of Computer Applications },
issue_date = { March 2013 },
volume = { 65 },
number = { 16 },
month = { March },
year = { 2013 },
issn = { 0975-8887 },
pages = { 36-38 },
numpages = {9},
url = { https://ijcaonline.org/archives/volume65/number16/11010-6344/ },
doi = { 10.5120/11010-6344 },
publisher = {Foundation of Computer Science (FCS), NY, USA},
address = {New York, USA}
}
%0 Journal Article
%1 2024-02-06T21:19:02.072492+05:30
%A Neha Agarwal
%A Satyajit Anand
%T Logical Effort to Study the Performance of 32-bit Heterogeneous Adder
%J International Journal of Computer Applications
%@ 0975-8887
%V 65
%N 16
%P 36-38
%D 2013
%I Foundation of Computer Science (FCS), NY, USA
Abstract

The method of Logical Effort is an easy way to estimate the delay in a CMOS circuit. In this work application of Logical Effort on transistor level analysis of 32-bit heterogeneous adder architecture is designed and presented. Heterogeneous architecture consists of concatenation of four different sub adders (Ripple Carry, Carry Look Ahead, Carry Skip and Carry Select Adder) to design an adder unit. The efficiency of the Logical Effort model is analyzed by circuit simulation using Tanner EDA Tool.

References
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  2. Sutherland, B. Sproull, D. Harris, Logical effort designing fast cmos circuit, Morgan Kaufmann publisher, 1st Edition,1999.
  3. Neha Agarwal, Satyajit Anand, "Study and performance comparison of VLSI adders using logical effort delay model," IJATER, Volume 2, Issue 6, Nov. 2012.
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  9. X. Yu, V. Oklobdzija, "Application of Logical Effort on Design of Arithmetic Blocks in VLSI CMOS Technology," 35th Asilomar Conference on Signals, Systems and Computers, Nov. 2001.
  10. H. Dao and V. G. Oklobdzija, "Application of Logical Effort on Delay Analysis of 64 - bit Static Carry Look- ahead Adder, " 35th Asilomar Conference on Signals, Systems and Computers, 2001.
  11. R. P Singh and A. Chaturvedi, "VLSI Implementation of Heterogeneous Adder for performance Optimization," International Journal of Computer Applications (0975-8887), Volume 51–No. 7, Aug. 2012.
Index Terms

Computer Science
Information Sciences

Keywords

Absolute Delay Electrical Effort Heterogeneous Adder Logical Effort Stage Effort

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